Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case		2017-09-29 11:56:43 +02:00
..
.gitignore
asserts.v
asserts.ys	Added read_verilog -sv options, added support for bit, logic,	2014-06-12 11:54:20 +02:00
asserts_seq.v
asserts_seq.ys	Added read_verilog -sv options, added support for bit, logic,	2014-06-12 11:54:20 +02:00
counters.v
counters.ys
expose_dff.v	Added test cases for expose -evert-dff	2014-02-08 21:31:56 +01:00
expose_dff.ys	Added test cases for expose -evert-dff	2014-02-08 21:31:56 +01:00
initval.v	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
initval.ys	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
run-test.sh
share.v	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
share.ys	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
sizebits.sv	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
sizebits.ys	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
splice.v	Added splice command	2014-02-07 20:30:56 +01:00
splice.ys	Added splice command	2014-02-07 20:30:56 +01:00