mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 01:14:37 +00:00
Code Activity
yosys/techlibs/intel
History
Marcelina Kościelnicka 082cbcb4c7 synth_intel: Remove incomplete Arria 10 GX support. 
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
2020-08-21 01:46:06 +02:00
..
common intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
cyclone10lp intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
cycloneiv intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
cycloneive intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
max10 intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Makefile.inc synth_intel: Remove incomplete Arria 10 GX support. 2020-08-21 01:46:06 +02:00
synth_intel.cc synth_intel: Remove incomplete Arria 10 GX support. 2020-08-21 01:46:06 +02:00