mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 12:28:44 +00:00
26 lines
851 B
Diff
26 lines
851 B
Diff
diff --git a/bench/bench.cpp b/bench/bench.cpp
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index 47a50c4..de27fbb 100755
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--- a/bench/bench.cpp
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+++ b/bench/bench.cpp
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@@ -71,6 +71,7 @@ int main(int argc, char **argv, char **env) {
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main_time++;
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top->arbclk_i = !top->arbclk_i;
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if (main_time%5 == 0) top->clk = !top->clk;
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+ if (main_time%100000 == 0) cout<<"Partial sum = "<<hex<<top->sum<<"\n";
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}
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cout<<"Final sum = "<<hex<<top->sum<<"\n";
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diff --git a/rtl/k68_clkgen.v b/rtl/k68_clkgen.v
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index c201a97..55b9cad 100755
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--- a/rtl/k68_clkgen.v
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+++ b/rtl/k68_clkgen.v
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@@ -57,7 +57,7 @@ module k68_clkgen (/*AUTOARG*/
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assign clk4_o = cnt[1];
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assign clk_o = ~clk_i;
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- initial cnt = 0; // Power up state doesn't matter, but can't be X
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+ // initial cnt = 0; // Power up state doesn't matter, but can't be X
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always @(posedge clk_i) begin
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cnt <= cnt + 1'b1;
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