mirror of
https://github.com/YosysHQ/yosys
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042b3074f8
This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
538 lines
17 KiB
C++
538 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#include "verilog_frontend.h"
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#include "kernel/yosys.h"
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#include "libs/sha1/sha1.h"
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#include <stdarg.h>
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YOSYS_NAMESPACE_BEGIN
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using namespace VERILOG_FRONTEND;
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// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
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static std::vector<std::string> verilog_defaults;
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static std::list<std::vector<std::string>> verilog_defaults_stack;
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static void error_on_dpi_function(AST::AstNode *node)
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{
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if (node->type == AST::AST_DPI_FUNCTION)
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log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str());
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for (auto child : node->children)
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error_on_dpi_function(child);
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}
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_verilog [options] [filename]\n");
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log("\n");
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log("Load modules from a Verilog file to the current design. A large subset of\n");
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log("Verilog-2005 is supported.\n");
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log("\n");
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log(" -sv\n");
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log(" enable support for SystemVerilog features. (only a small subset\n");
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log(" of SystemVerilog is supported)\n");
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log("\n");
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log(" -formal\n");
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log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
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log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
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log("\n");
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log(" -norestrict\n");
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log(" ignore restrict() assertions\n");
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log("\n");
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log(" -assume-asserts\n");
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log(" treat all assert() statements like assume() statements\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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log("\n");
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log(" -dump_ast2\n");
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -no_dump_ptr\n");
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log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
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log("\n");
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log(" -dump_vlog\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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log(" -dump_rtlil\n");
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log(" dump generated RTLIL netlist\n");
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log("\n");
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log(" -yydebug\n");
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log(" enable parser debug output\n");
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log("\n");
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log(" -nolatches\n");
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log(" usually latches are synthesized into logic loops\n");
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log(" this option prohibits this and sets the output to 'x'\n");
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log(" in what would be the latches hold condition\n");
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log("\n");
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log(" this behavior can also be achieved by setting the\n");
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log(" 'nolatches' attribute on the respective module or\n");
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log(" always block.\n");
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log("\n");
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log(" -nomem2reg\n");
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log(" under certain conditions memories are converted to registers\n");
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log(" early during simplification to ensure correct handling of\n");
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log(" complex corner cases. this option disables this behavior.\n");
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log("\n");
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log(" this can also be achieved by setting the 'nomem2reg'\n");
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log(" attribute on the respective module or register.\n");
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log("\n");
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log(" This is potentially dangerous. Usually the front-end has good\n");
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log(" reasons for converting an array to a list of registers.\n");
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log(" Prohibiting this step will likely result in incorrect synthesis\n");
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log(" results.\n");
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log("\n");
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log(" -mem2reg\n");
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log(" always convert memories to registers. this can also be\n");
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log(" achieved by setting the 'mem2reg' attribute on the respective\n");
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log(" module or register.\n");
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log("\n");
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log(" -nomeminit\n");
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log(" do not infer $meminit cells and instead convert initialized\n");
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log(" memories to registers directly in the front-end.\n");
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log("\n");
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log(" -ppdump\n");
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log(" dump Verilog code after pre-processor\n");
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log("\n");
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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log(" -nodpi\n");
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log(" disable DPI-C support\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
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log("\n");
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log(" -noopt\n");
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log(" don't perform basic optimizations (such as const folding) in the\n");
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log(" high-level front-end.\n");
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log("\n");
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log(" -icells\n");
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log(" interpret cell types starting with '$' as internal cell types\n");
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log("\n");
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log(" -nooverwrite\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message if the existing module is not a black box\n");
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log(" module, and overwrite the existing module otherwise.)\n");
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log("\n");
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log(" -overwrite\n");
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log(" overwrite existing modules with the same name\n");
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log("\n");
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log(" -defer\n");
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log(" only read the abstract syntax tree and defer actual compilation\n");
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log(" to a later 'hierarchy' command. Useful in cases where the default\n");
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log(" parameters of modules yield invalid or not synthesizable code.\n");
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log("\n");
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log(" -noautowire\n");
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log(" make the default of `default_nettype be \"none\" instead of \"wire\".\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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log(" -Dname[=definition]\n");
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log(" define the preprocessor symbol 'name' and set its optional value\n");
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log(" 'definition'\n");
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log("\n");
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log(" -Idir\n");
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log(" add 'dir' to the directories which are used when searching include\n");
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log(" files\n");
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log("\n");
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log("The command 'verilog_defaults' can be used to register default options for\n");
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log("subsequent calls to 'read_verilog'.\n");
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log("\n");
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log("Note that the Verilog frontend does a pretty good job of processing valid\n");
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log("verilog input, but has not very good error reporting. It generally is\n");
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log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
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log("the syntax of the code, rather than to rely on read_verilog for that.\n");
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log("\n");
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log("Depending on if read_verilog is run in -formal mode, either the macro\n");
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log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n");
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log("always defines the macro YOSYS.\n");
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log("\n");
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log("See the Yosys README file for a list of non-standard Verilog features\n");
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log("supported by the Yosys Verilog front-end.\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_no_dump_ptr = false;
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bool flag_dump_vlog = false;
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bool flag_dump_rtlil = false;
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bool flag_nolatches = false;
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bool flag_nomeminit = false;
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bool flag_nomem2reg = false;
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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bool flag_nodpi = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_defer = false;
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std::map<std::string, std::string> defines_map;
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std::list<std::string> include_dirs;
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std::list<std::string> attributes;
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frontend_verilog_yydebug = false;
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sv_mode = false;
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formal_mode = false;
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norestrict_mode = false;
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assume_asserts_mode = false;
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lib_mode = false;
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default_nettype_wire = true;
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log_header(design, "Executing Verilog-2005 frontend.\n");
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args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-sv") {
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sv_mode = true;
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continue;
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}
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if (arg == "-formal") {
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formal_mode = true;
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continue;
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}
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if (arg == "-norestrict") {
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norestrict_mode = true;
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continue;
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}
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if (arg == "-assume-asserts") {
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assume_asserts_mode = true;
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continue;
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}
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if (arg == "-dump_ast1") {
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flag_dump_ast1 = true;
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continue;
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}
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if (arg == "-dump_ast2") {
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flag_dump_ast2 = true;
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continue;
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}
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if (arg == "-no_dump_ptr") {
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flag_no_dump_ptr = true;
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continue;
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}
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if (arg == "-dump_vlog") {
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flag_dump_vlog = true;
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continue;
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}
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if (arg == "-dump_rtlil") {
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flag_dump_rtlil = true;
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continue;
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}
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if (arg == "-yydebug") {
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frontend_verilog_yydebug = true;
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continue;
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}
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if (arg == "-nolatches") {
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flag_nolatches = true;
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continue;
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}
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if (arg == "-nomeminit") {
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flag_nomeminit = true;
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continue;
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}
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if (arg == "-nomem2reg") {
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flag_nomem2reg = true;
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continue;
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}
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if (arg == "-mem2reg") {
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flag_mem2reg = true;
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continue;
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}
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if (arg == "-ppdump") {
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flag_ppdump = true;
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continue;
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}
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if (arg == "-nopp") {
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flag_nopp = true;
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continue;
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}
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if (arg == "-nodpi") {
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flag_nodpi = true;
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continue;
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}
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if (arg == "-lib") {
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lib_mode = true;
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defines_map["BLACKBOX"] = string();
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continue;
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}
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if (arg == "-noopt") {
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flag_noopt = true;
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continue;
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}
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if (arg == "-icells") {
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flag_icells = true;
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continue;
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}
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if (arg == "-ignore_redef" || arg == "-nooverwrite") {
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flag_nooverwrite = true;
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flag_overwrite = false;
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continue;
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}
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if (arg == "-overwrite") {
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flag_nooverwrite = false;
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flag_overwrite = true;
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continue;
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}
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if (arg == "-defer") {
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flag_defer = true;
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continue;
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}
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if (arg == "-noautowire") {
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default_nettype_wire = false;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (arg == "-D" && argidx+1 < args.size()) {
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std::string name = args[++argidx], value;
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size_t equal = name.find('=');
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if (equal != std::string::npos) {
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value = name.substr(equal+1);
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name = name.substr(0, equal);
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}
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defines_map[name] = value;
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continue;
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}
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if (arg.compare(0, 2, "-D") == 0) {
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size_t equal = arg.find('=', 2);
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std::string name = arg.substr(2, equal-2);
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std::string value;
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if (equal != std::string::npos)
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value = arg.substr(equal+1);
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defines_map[name] = value;
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continue;
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}
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if (arg == "-I" && argidx+1 < args.size()) {
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include_dirs.push_back(args[++argidx]);
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continue;
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}
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if (arg.compare(0, 2, "-I") == 0) {
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include_dirs.push_back(arg.substr(2));
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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log("Parsing %s%s input from `%s' to AST representation.\n",
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formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
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AST::current_filename = filename;
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AST::set_line_num = &frontend_verilog_yyset_lineno;
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AST::get_line_num = &frontend_verilog_yyget_lineno;
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current_ast = new AST::AstNode(AST::AST_DESIGN);
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lexin = f;
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std::string code_after_preproc;
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if (!flag_nopp) {
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code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, design->verilog_defines, include_dirs);
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if (flag_ppdump)
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log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
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lexin = new std::istringstream(code_after_preproc);
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}
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frontend_verilog_yyset_lineno(1);
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frontend_verilog_yyrestart(NULL);
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frontend_verilog_yyparse();
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frontend_verilog_yylex_destroy();
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for (auto &child : current_ast->children) {
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if (child->type == AST::AST_MODULE)
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for (auto &attr : attributes)
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if (child->attributes.count(attr) == 0)
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child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
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}
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if (flag_nodpi)
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error_on_dpi_function(current_ast);
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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if (!flag_nopp)
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delete lexin;
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delete current_ast;
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current_ast = NULL;
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log("Successfully finished Verilog frontend.\n");
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}
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} VerilogFrontend;
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struct VerilogDefaults : public Pass {
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VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" verilog_defaults -add [options]\n");
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log("\n");
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log("Add the specified options to the list of default options to read_verilog.\n");
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log("\n");
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log("\n");
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log(" verilog_defaults -clear\n");
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log("\n");
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log("Clear the list of Verilog default options.\n");
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log("\n");
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log("\n");
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log(" verilog_defaults -push\n");
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log(" verilog_defaults -pop\n");
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log("\n");
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log("Push or pop the list of default options to a stack. Note that -push does\n");
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log("not imply -clear.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
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{
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if (args.size() < 2)
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cmd_error(args, 1, "Missing argument.");
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if (args[1] == "-add") {
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verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
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return;
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}
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if (args.size() != 2)
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cmd_error(args, 2, "Extra argument.");
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if (args[1] == "-clear") {
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verilog_defaults.clear();
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return;
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}
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if (args[1] == "-push") {
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verilog_defaults_stack.push_back(verilog_defaults);
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return;
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}
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if (args[1] == "-pop") {
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if (verilog_defaults_stack.empty()) {
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verilog_defaults.clear();
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} else {
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verilog_defaults.swap(verilog_defaults_stack.back());
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verilog_defaults_stack.pop_back();
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}
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return;
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}
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}
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} VerilogDefaults;
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struct VerilogDefines : public Pass {
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VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" verilog_defines [options]\n");
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log("\n");
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log("Define and undefine verilog preprocessor macros.\n");
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log("\n");
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log(" -Dname[=definition]\n");
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log(" define the preprocessor symbol 'name' and set its optional value\n");
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log(" 'definition'\n");
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log("\n");
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log(" -Uname[=definition]\n");
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|
log(" undefine the preprocessor symbol 'name'\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-D" && argidx+1 < args.size()) {
|
|
std::string name = args[++argidx], value;
|
|
size_t equal = name.find('=');
|
|
if (equal != std::string::npos) {
|
|
value = name.substr(equal+1);
|
|
name = name.substr(0, equal);
|
|
}
|
|
design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
|
|
continue;
|
|
}
|
|
if (arg.compare(0, 2, "-D") == 0) {
|
|
size_t equal = arg.find('=', 2);
|
|
std::string name = arg.substr(2, equal-2);
|
|
std::string value;
|
|
if (equal != std::string::npos)
|
|
value = arg.substr(equal+1);
|
|
design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
|
|
continue;
|
|
}
|
|
if (arg == "-U" && argidx+1 < args.size()) {
|
|
std::string name = args[++argidx];
|
|
design->verilog_defines.erase(name);
|
|
continue;
|
|
}
|
|
if (arg.compare(0, 2, "-U") == 0) {
|
|
std::string name = arg.substr(2);
|
|
design->verilog_defines.erase(name);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (args.size() != argidx)
|
|
cmd_error(args, argidx, "Extra argument.");
|
|
}
|
|
} VerilogDefines;
|
|
|
|
YOSYS_NAMESPACE_END
|
|
|
|
// the yyerror function used by bison to report parser errors
|
|
void frontend_verilog_yyerror(char const *fmt, ...)
|
|
{
|
|
va_list ap;
|
|
char buffer[1024];
|
|
char *p = buffer;
|
|
va_start(ap, fmt);
|
|
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
|
|
va_end(ap);
|
|
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
|
|
YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
|
|
"%s", buffer);
|
|
exit(1);
|
|
}
|