mirror of
https://github.com/YosysHQ/yosys
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d1b767ea8b
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip design for my Sipeed Tang FPGA fails. |
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| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_gowin.cc | ||