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yosys/passes
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Marcelina Kościelnicka 03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
..
cmds Add new builtin FF types 2020-06-23 15:40:02 +02:00
equiv Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
memory Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
opt opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 2020-07-05 06:31:58 +02:00
pmgen Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused). 2020-06-19 15:48:58 +00:00
proc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
sat clk2fflogic: Consistently treat async control signals as negative hold. 2020-07-09 18:12:47 +02:00
techmap dfflegalize: Add special support for const-D latches. 2020-07-09 18:11:32 +02:00
tests Merge pull request #2201 from YosysHQ/fix_test_cell_ilang 2020-06-30 17:11:13 +02:00