mirror of
https://github.com/YosysHQ/yosys
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58 lines
1.2 KiB
Tcl
58 lines
1.2 KiB
Tcl
# Run with "libero SCRIPT:libero.tcl"
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file delete -force proj
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new_project \
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-name example \
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-location proj \
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-block_mode 0 \
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-hdl "VERILOG" \
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-family IGLOO2 \
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-die PA4MGL2500 \
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-package vf256 \
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-speed -1
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import_files -hdl_source {netlist.vm}
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import_files -sdc {example.sdc}
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import_files -io_pdc {example.pdc}
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build_design_hierarchy
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set_option -synth 0
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organize_tool_files -tool PLACEROUTE \
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-file {proj/constraint/example.sdc} \
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-file {proj/constraint/io/example.pdc} \
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-input_type constraint
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organize_tool_files -tool VERIFYTIMING \
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-file {proj/constraint/example.sdc} \
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-input_type constraint
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configure_tool -name PLACEROUTE \
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-params TDPR:true \
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-params PDPR:false \
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-params EFFORT_LEVEL:false \
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-params REPAIR_MIN_DELAY:false
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puts ""
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puts "**> COMPILE"
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run_tool -name {COMPILE}
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puts "<** COMPILE"
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puts ""
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puts "**> PLACEROUTE"
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run_tool -name {PLACEROUTE}
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puts "<** PLACEROUTE"
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puts ""
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puts "**> VERIFYTIMING"
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run_tool -name {VERIFYTIMING}
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puts "<** VERIFYTIMING"
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puts ""
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puts "**> BITSTREAM"
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export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
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puts "<** BITSTREAM"
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puts ""
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exit 0
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