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https://github.com/YosysHQ/yosys
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45 lines
1.8 KiB
Text
45 lines
1.8 KiB
Text
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List of incompatible changes and major milestones between releases
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==================================================================
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Yosys 0.1.0 .. Yoys 0.1.0+
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--------------------------
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* Improvements in Verilog frontend:
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- Added support for local registers in named blocks
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- Added support for "case" in "generate" blocks
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- Added support for $clog2 system function
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- Added preprocessor support for macro arguments
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- Added preprocessor support for `elsif statement
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* Improvements in technology mapping:
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- The "dfflibmap" command now strongly prefers solutions with
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no inverters in clock paths
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- The "dfflibmap" command now prefers cells with smaller area
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* Integration with ABC:
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- Updated ABC to hg rev 57517e81666b
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- Tighter integration of ABC build with Yosys build. The make
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targets 'make abc' and 'make install-abc' are now obsolete.
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- Added support for passing FFs from one clock domain through ABC
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- Now always use BLIF as exchange format with ABC
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* Improvements to "eval" and "sat" framework:
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- Added support for "0" and "~0" in right-hand side -set expressions
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- Added "eval -set-undef" and "eval -table"
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- Added "sat -set-init" support for sequential problems
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- Added undef support to SAT solver, incl. various new "sat" options
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- Added correct support for === and !== for "eval" and "sat"
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* Added "abbreviated IDs":
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- Now $<something>$foo can be abbriviated as $foo.
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- Usually this last part is a unique id (from RTLIL::autoidx)
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- This abbreviated IDs are now also used in "show" output
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* Various other changes to commands and options:
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- The "ls" command now supports wildcards
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- Added "show -pause" and "show -format dot"
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- Added "dump -m" and "dump -n"
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- Added "history" command
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