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45 lines
550 B
Verilog
45 lines
550 B
Verilog
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module test01(a, b, x, y, z);
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input [7:0] a;
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input [2:0] b;
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output [7:0] x, y;
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output z;
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assign x = a >> b;
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assign y = a[b+7:b];
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assign z = a[b];
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endmodule
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module test02(clk, a, b, x, y, z);
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input clk;
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input [7:0] a;
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input [2:0] b;
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output reg [7:0] x, y;
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output reg z;
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always @(posedge clk) begin
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x <= a >> b;
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y <= a[b+7:b];
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z <= a[b];
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end
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endmodule
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module test03(clk, a, b, x, y);
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input clk;
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input [2:0] a, b;
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output reg [7:0] x;
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output reg [9:0] y;
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always @(posedge clk)
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y[b] <= a;
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always @(posedge clk)
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y[b+2:b] <= a;
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endmodule
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