mirror of
https://github.com/YosysHQ/yosys
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30 lines
964 B
Bash
30 lines
964 B
Bash
#!/bin/bash
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if (
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set -ex
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cd verilog-sim-benchmarks
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rm -rf obj_dir_* synth
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cd rtl
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mkdir -p ../synth
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../../../../yosys -o ../synth/k68_soc.v -p 'hierarchy -check -top k68_soc; proc; opt; memory; opt' \
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k68_soc.v k68_arb.v k68_cpu.v k68_load.v k68_clkgen.v k68_decode.v k68_execute.v \
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k68_fetch.v k68_regbank.v k68_buni.v k68_b2d.v k68_ccc.v k68_d2b.v k68_rox.v \
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k68_calc.v k68_dpmem.v k68_sasc.v sasc_brg.v sasc_top.v sasc_fifo4.v
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cd ..
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VERILATOR_OPT="-Wno-fatal -Ibench --cc bench/k68_soc_test.v --exe bench/bench.cpp -prefix m68 -x-assign 0"
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verilator -Mdir obj_dir_rtl -Irtl $VERILATOR_OPT; make -C obj_dir_rtl -f m68.mk
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verilator -Mdir obj_dir_synth -Isynth $VERILATOR_OPT; make -C obj_dir_synth -f m68.mk
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./obj_dir_rtl/m68 100000 | tee output_rtl.txt
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./obj_dir_synth/m68 100000 | tee output_synth.txt
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diff -u <( grep ' sum ' output_rtl.txt; ) <( grep ' sum ' output_synth.txt; )
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); then
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echo OK
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exit 0
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else
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echo ERROR
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exit 1
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fi
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