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02e40e8118
UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf specifies that the only flip-flop types supported in GW5 are DFFSE, DFFRE, DFFPE, and DFFCE. However, the bit streams generated by the vendor IDE also contain DFF flip-flops, which are probably the result of optimisation, so we leave them in the list of permitted items, but add a flag that will allow the generation of completely correct output files, acceptable for further P& R using vendor tools (they will not allow the use of flip-flops other than the four specified in the netlist). In the GW5 SemiDual Port BSRAM series, the primitive does not have RESETA and RESETB ports—they are replaced by the RESET port, so we separate the files for BSRAM generation, especially since in the future we may have to take into account other, as yet unexplored, differences in BSRAM. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
399 lines
8.4 KiB
Verilog
399 lines
8.4 KiB
Verilog
`define DEF_FUNCS \
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function [255:0] init_slice_x8; \
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input integer idx; \
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integer i; \
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for (i = 0; i < 32; i = i + 1) begin \
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init_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \
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end \
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endfunction \
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function [287:0] init_slice_x9; \
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input integer idx; \
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init_slice_x9 = INIT[idx * 288+:288]; \
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endfunction \
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`define x8_width(width) (width / 9 * 8 + width % 9)
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`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
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`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
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`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})
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`define INIT(func) \
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.INIT_RAM_00(func('h00)), \
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.INIT_RAM_01(func('h01)), \
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.INIT_RAM_02(func('h02)), \
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.INIT_RAM_03(func('h03)), \
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.INIT_RAM_04(func('h04)), \
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.INIT_RAM_05(func('h05)), \
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.INIT_RAM_06(func('h06)), \
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.INIT_RAM_07(func('h07)), \
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.INIT_RAM_08(func('h08)), \
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.INIT_RAM_09(func('h09)), \
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.INIT_RAM_0A(func('h0a)), \
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.INIT_RAM_0B(func('h0b)), \
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.INIT_RAM_0C(func('h0c)), \
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.INIT_RAM_0D(func('h0d)), \
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.INIT_RAM_0E(func('h0e)), \
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.INIT_RAM_0F(func('h0f)), \
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.INIT_RAM_10(func('h10)), \
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.INIT_RAM_11(func('h11)), \
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.INIT_RAM_12(func('h12)), \
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.INIT_RAM_13(func('h13)), \
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.INIT_RAM_14(func('h14)), \
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.INIT_RAM_15(func('h15)), \
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.INIT_RAM_16(func('h16)), \
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.INIT_RAM_17(func('h17)), \
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.INIT_RAM_18(func('h18)), \
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.INIT_RAM_19(func('h19)), \
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.INIT_RAM_1A(func('h1a)), \
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.INIT_RAM_1B(func('h1b)), \
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.INIT_RAM_1C(func('h1c)), \
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.INIT_RAM_1D(func('h1d)), \
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.INIT_RAM_1E(func('h1e)), \
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.INIT_RAM_1F(func('h1f)), \
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.INIT_RAM_20(func('h20)), \
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.INIT_RAM_21(func('h21)), \
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.INIT_RAM_22(func('h22)), \
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.INIT_RAM_23(func('h23)), \
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.INIT_RAM_24(func('h24)), \
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.INIT_RAM_25(func('h25)), \
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.INIT_RAM_26(func('h26)), \
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.INIT_RAM_27(func('h27)), \
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.INIT_RAM_28(func('h28)), \
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.INIT_RAM_29(func('h29)), \
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.INIT_RAM_2A(func('h2a)), \
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.INIT_RAM_2B(func('h2b)), \
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.INIT_RAM_2C(func('h2c)), \
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.INIT_RAM_2D(func('h2d)), \
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.INIT_RAM_2E(func('h2e)), \
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.INIT_RAM_2F(func('h2f)), \
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.INIT_RAM_30(func('h30)), \
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.INIT_RAM_31(func('h31)), \
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.INIT_RAM_32(func('h32)), \
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.INIT_RAM_33(func('h33)), \
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.INIT_RAM_34(func('h34)), \
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.INIT_RAM_35(func('h35)), \
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.INIT_RAM_36(func('h36)), \
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.INIT_RAM_37(func('h37)), \
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.INIT_RAM_38(func('h38)), \
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.INIT_RAM_39(func('h39)), \
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.INIT_RAM_3A(func('h3a)), \
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.INIT_RAM_3B(func('h3b)), \
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.INIT_RAM_3C(func('h3c)), \
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.INIT_RAM_3D(func('h3d)), \
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.INIT_RAM_3E(func('h3e)), \
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.INIT_RAM_3F(func('h3f)),
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module $__GOWIN_SP_ (...);
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parameter INIT = 0;
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parameter OPTION_RESET_MODE = "SYNC";
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parameter PORT_A_WIDTH = 36;
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parameter PORT_A_OPTION_WRITE_MODE = 0;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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`DEF_FUNCS
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wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
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wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
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generate
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if (PORT_A_WIDTH < 9) begin
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wire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);
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wire [31:0] DO;
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assign PORT_A_RD_DATA = `x8_rd_data(DO);
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SP #(
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`INIT(init_slice_x8)
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.READ_MODE(1'b0),
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.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
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.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),
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.BLK_SEL(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSEL(3'b000),
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.CLK(PORT_A_CLK),
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.CE(PORT_A_CLK_EN),
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.WRE(PORT_A_WR_EN),
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.RESET(RST),
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.OCE(1'b1),
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.AD(AD),
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.DI(DI),
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.DO(DO),
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);
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end else begin
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wire [35:0] DI = PORT_A_WR_DATA;
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wire [35:0] DO;
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assign PORT_A_RD_DATA = DO;
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SPX9 #(
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`INIT(init_slice_x9)
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.READ_MODE(1'b0),
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.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
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.BIT_WIDTH(PORT_A_WIDTH),
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.BLK_SEL(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSEL(3'b000),
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.CLK(PORT_A_CLK),
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.CE(PORT_A_CLK_EN),
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.WRE(PORT_A_WR_EN),
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.RESET(RST),
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.OCE(1'b1),
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.AD(AD),
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.DI(DI),
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.DO(DO),
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);
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end
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endgenerate
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endmodule
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module $__GOWIN_DP_ (...);
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parameter INIT = 0;
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parameter OPTION_RESET_MODE = "SYNC";
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parameter PORT_A_WIDTH = 18;
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parameter PORT_A_OPTION_WRITE_MODE = 0;
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parameter PORT_B_WIDTH = 18;
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parameter PORT_B_OPTION_WRITE_MODE = 0;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [13:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [13:0] PORT_B_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
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`DEF_FUNCS
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wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
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wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
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wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
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wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);
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generate
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if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
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wire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);
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wire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);
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wire [15:0] DOA;
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wire [15:0] DOB;
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assign PORT_A_RD_DATA = `x8_rd_data(DOA);
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assign PORT_B_RD_DATA = `x8_rd_data(DOB);
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DPB #(
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`INIT(init_slice_x8)
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.READ_MODE0(1'b0),
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.READ_MODE1(1'b0),
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.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
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.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
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.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),
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.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),
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.BLK_SEL_0(3'b000),
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.BLK_SEL_1(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSELA(3'b000),
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.BLKSELB(3'b000),
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.CLKA(PORT_A_CLK),
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.CEA(PORT_A_CLK_EN),
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.WREA(PORT_A_WR_EN),
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.RESETA(RSTA),
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.OCEA(1'b1),
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.ADA(ADA),
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.DIA(DIA),
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.DOA(DOA),
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.CLKB(PORT_B_CLK),
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.CEB(PORT_B_CLK_EN),
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.WREB(PORT_B_WR_EN),
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.RESETB(RSTB),
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.OCEB(1'b1),
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.ADB(ADB),
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.DIB(DIB),
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.DOB(DOB),
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);
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end else begin
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wire [17:0] DIA = PORT_A_WR_DATA;
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wire [17:0] DIB = PORT_B_WR_DATA;
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wire [17:0] DOA;
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wire [17:0] DOB;
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assign PORT_A_RD_DATA = DOA;
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assign PORT_B_RD_DATA = DOB;
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DPX9B #(
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`INIT(init_slice_x9)
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.READ_MODE0(1'b0),
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.READ_MODE1(1'b0),
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.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
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.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
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.BIT_WIDTH_0(PORT_A_WIDTH),
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.BIT_WIDTH_1(PORT_B_WIDTH),
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.BLK_SEL_0(3'b000),
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.BLK_SEL_1(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSELA(3'b000),
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.BLKSELB(3'b000),
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.CLKA(PORT_A_CLK),
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.CEA(PORT_A_CLK_EN),
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.WREA(PORT_A_WR_EN),
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.RESETA(RSTA),
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.OCEA(1'b1),
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.ADA(ADA),
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.DIA(DIA),
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.DOA(DOA),
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.CLKB(PORT_B_CLK),
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.CEB(PORT_B_CLK_EN),
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.WREB(PORT_B_WR_EN),
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.RESETB(RSTB),
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.OCEB(1'b1),
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.ADB(ADB),
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.DIB(DIB),
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.DOB(DOB),
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);
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end
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endgenerate
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endmodule
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module $__GOWIN_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_RESET_MODE = "SYNC";
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parameter PORT_R_WIDTH = 18;
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parameter PORT_W_WIDTH = 18;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input PORT_R_RD_SRST;
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input PORT_R_RD_ARST;
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input [13:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input PORT_W_WR_EN;
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input [13:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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`DEF_FUNCS
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wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
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wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
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wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
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generate
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if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
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wire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);
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wire [31:0] DO;
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assign PORT_R_RD_DATA = `x8_rd_data(DO);
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SDPB #(
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`INIT(init_slice_x8)
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.READ_MODE(1'b0),
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.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),
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.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),
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.BLK_SEL_0(3'b000),
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.BLK_SEL_1(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSELA(3'b000),
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.BLKSELB(3'b000),
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.CLKA(PORT_W_CLK),
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.CEA(WRE),
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.ADA(ADW),
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.DI(DI),
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.CLKB(PORT_R_CLK),
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.CEB(PORT_R_CLK_EN),
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.RESET(RST),
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.OCE(1'b1),
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.ADB(PORT_R_ADDR),
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.DO(DO),
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);
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end else begin
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wire [35:0] DI = PORT_W_WR_DATA;
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wire [35:0] DO;
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assign PORT_R_RD_DATA = DO;
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SDPX9B #(
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`INIT(init_slice_x9)
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.READ_MODE(1'b0),
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.BIT_WIDTH_0(PORT_W_WIDTH),
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.BIT_WIDTH_1(PORT_R_WIDTH),
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.BLK_SEL_0(3'b000),
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.BLK_SEL_1(3'b000),
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.RESET_MODE(OPTION_RESET_MODE),
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) _TECHMAP_REPLACE_ (
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.BLKSELA(3'b000),
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.BLKSELB(3'b000),
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.CLKA(PORT_W_CLK),
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.CEA(WRE),
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.ADA(ADW),
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.DI(DI),
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.CLKB(PORT_R_CLK),
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.CEB(PORT_R_CLK_EN),
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.RESET(RST),
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.OCE(1'b1),
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.ADB(PORT_R_ADDR),
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.DO(DO),
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);
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end
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endgenerate
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endmodule
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