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yosys/backends/cxxrtl
Catherine 02e3d508fa cxxrtl: remove module::steps. (breaking change)
This approach to tracking simulation time was a mistake that I did not
catch in review. It has several issues:
1. There is absolutely no requirement to call `step()`, as it is
   a convenience function. In particular, `steps` will not be
   incremented in submodules if `-noflatten` is used.
2. The semantics of `steps` does not match that of the Verilog `$time`
   construct.
3. There is no way to make the semantics of `%t` match that of Verilog.
4. The `module` interface is intentionally very barebones. It is little
   more than a container for three method pointers, `reset`, `eval`,
   and `commit`. Adding ancillary data to it goes against this.

If similar functionality is introduced again it should probably be
a variable that is global per toplevel design using some object that is
unique for an entire hierarchy of modules, and ideally exposed via
the C API. For now, it is being removed (in this commit) and (in next
commit) the capability is being reintroduced through a context object
that can be specified for `eval()`.
2024-01-16 16:35:51 +00:00
..
runtime cxxrtl: remove module::steps. (breaking change) 2024-01-16 16:35:51 +00:00
cxxrtl_backend.cc cxxrtl: remove module::steps. (breaking change) 2024-01-16 16:35:51 +00:00
Makefile.inc cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 2020-06-07 03:48:40 +00:00