mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 13:29:12 +00:00
4b2f977331
This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
29 lines
421 B
Text
29 lines
421 B
Text
read_verilog -nomem2reg port_sign_extend.v
|
|
hierarchy
|
|
flatten
|
|
proc
|
|
memory
|
|
equiv_make ref act equiv
|
|
equiv_simple
|
|
equiv_status -assert
|
|
|
|
delete
|
|
|
|
read_verilog -nomem2reg port_sign_extend.v
|
|
flatten
|
|
proc
|
|
memory
|
|
equiv_make ref act equiv
|
|
equiv_simple
|
|
equiv_status -assert
|
|
|
|
delete
|
|
|
|
read_verilog -nomem2reg port_sign_extend.v
|
|
hierarchy
|
|
proc
|
|
memory
|
|
equiv_make ref act equiv
|
|
prep -flatten -top equiv
|
|
equiv_induct
|
|
equiv_status -assert
|