Dag Lem a460e0b31c Tests for unpacked arrays in packed structs are for the Yosys frontend only		2022-11-23 16:37:51 +01:00
..
.gitignore
enum_simple.sv
enum_simple.ys
logic_rom.sv
logic_rom.ys	Add v2 memory cells.	2021-08-11 13:34:10 +02:00
multirange_array.sv
multirange_subarray_access.ys
run-test.sh
static_cast_negative.ys
static_cast_nonconst.ys
static_cast_simple.sv
static_cast_verilog.ys
static_cast_zero.ys
struct_array.sv	Tests for unpacked arrays in packed structs are for the Yosys frontend only	2022-11-23 16:37:51 +01:00
struct_simple.sv
typedef_initial_and_assign.sv	sv: improve support for wire and var with user-defined types	2021-08-12 22:41:41 -06:00
typedef_initial_and_assign.ys	sv: improve support for wire and var with user-defined types	2021-08-12 22:41:41 -06:00
typedef_memory.sv
typedef_memory.ys	Add v2 memory cells.	2021-08-11 13:34:10 +02:00
typedef_memory_2.sv
typedef_memory_2.ys	Add v2 memory cells.	2021-08-11 13:34:10 +02:00
typedef_package.sv
typedef_param.sv
typedef_scopes.sv	verilog: check entire user type stack for type definition	2021-03-21 19:35:13 -04:00
typedef_simple.sv
typedef_struct.sv
typedef_struct_port.sv
typedef_struct_port.ys
union_simple.sv