mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
46 lines
1.6 KiB
Text
46 lines
1.6 KiB
Text
read_verilog ../common/mux.v
|
|
design -save read
|
|
|
|
hierarchy -top mux2
|
|
proc
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux2 # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:LUT4
|
|
select -assert-none t:LUT4 %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top mux4
|
|
proc
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux4 # Constrain all select calls below inside the top module
|
|
select -assert-max 1 t:L6MUX21
|
|
select -assert-max 4 t:LUT4
|
|
select -assert-max 2 t:PFUMX
|
|
|
|
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top mux8
|
|
proc
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux8 # Constrain all select calls below inside the top module
|
|
select -assert-max 1 t:L6MUX21
|
|
select -assert-max 8 t:LUT4
|
|
select -assert-max 3 t:PFUMX
|
|
|
|
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top mux16
|
|
proc
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux16 # Constrain all select calls below inside the top module
|
|
select -assert-max 12 t:L6MUX21
|
|
select -assert-max 34 t:LUT4
|
|
select -assert-max 17 t:PFUMX
|
|
|
|
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
|