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https://github.com/YosysHQ/yosys
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35 lines
1 KiB
Verilog
35 lines
1 KiB
Verilog
`default_nettype none
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module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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integer i,j;
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// Initialize in initial block as a workaround for
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// https://github.com/YosysHQ/yosys/issues/4792
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initial begin
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j = 64'hF4B1CA8127865242;
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for (i = 0; i <= DEPTH; i++) begin
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// In case this ROM will be implemented in fabric: fill the memory with some data
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// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
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// emit any LUTs at all for `memory[i] = i;`, just a latch.
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memory[i] = j * 64'h2545F4914F6CDD1D;
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j = j ^ (j >> 12);
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j = j ^ (j << 25);
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j = j ^ (j >> 27);
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end
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end
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always @(posedge clk) begin
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_rom
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