mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
36 lines
366 B
Verilog
36 lines
366 B
Verilog
module inv (
|
|
output Q,
|
|
input A
|
|
);
|
|
assign Q = A ? 0 : 1;
|
|
endmodule
|
|
|
|
module buff (
|
|
output Q,
|
|
input A
|
|
);
|
|
assign Q = A;
|
|
endmodule
|
|
|
|
module logic_0 (
|
|
output A
|
|
);
|
|
assign A = 0;
|
|
endmodule
|
|
|
|
module logic_1 (
|
|
output A
|
|
);
|
|
assign A = 1;
|
|
endmodule
|
|
|
|
module gclkbuff (
|
|
input A,
|
|
output Z
|
|
);
|
|
specify
|
|
(A => Z) = 0;
|
|
endspecify
|
|
|
|
assign Z = A;
|
|
endmodule
|