mirror of
https://github.com/YosysHQ/yosys
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201 lines
3.8 KiB
Verilog
201 lines
3.8 KiB
Verilog
module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA
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, BA);
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input [15:0] AA;
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input ACK;
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input ACKD;
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input ACKR;
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output ACOR;
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input ACS;
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output AERR;
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input [23:0] AI;
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output [23:0] AO;
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input AR;
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input AWE;
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input [15:0] BA;
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input BCK;
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input BCKD;
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input BCKR;
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output BCOR;
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input BCS;
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output BERR;
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input [23:0] BI;
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output [23:0] BO;
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input BR;
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input BWE;
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parameter mcka_edge = 1'b0;
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parameter mckb_edge = 1'b0;
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parameter mem_ctxt = "";
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parameter pcka_edge = 1'b0;
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parameter pckb_edge = 1'b0;
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parameter pipe_ia = 1'b0;
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parameter pipe_ib = 1'b0;
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parameter pipe_oa = 1'b0;
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parameter pipe_ob = 1'b0;
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parameter raw_config0 = 4'b0000;
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parameter raw_config1 = 16'b0000000000000000;
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parameter std_mode = "";
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NX_RAM #(
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.mcka_edge(mcka_edge),
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.mckb_edge(mckb_edge),
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.mem_ctxt(mem_ctxt),
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.pcka_edge(pcka_edge),
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.pckb_edge(pckb_edge),
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.pipe_ia(pipe_ia),
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.pipe_ib(pipe_ib),
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.pipe_oa(pipe_oa),
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.pipe_ob(pipe_ob),
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.raw_config0(raw_config0),
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.raw_config1(raw_config1),
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.std_mode(std_mode)
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) ram (
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.AA1(AA[0]),
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.AA10(AA[9]),
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.AA11(AA[10]),
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.AA12(AA[11]),
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.AA13(AA[12]),
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.AA14(AA[13]),
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.AA15(AA[14]),
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.AA16(AA[15]),
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.AA2(AA[1]),
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.AA3(AA[2]),
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.AA4(AA[3]),
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.AA5(AA[4]),
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.AA6(AA[5]),
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.AA7(AA[6]),
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.AA8(AA[7]),
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.AA9(AA[8]),
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.ACK(ACK),
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.ACKC(ACK),
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.ACKD(ACKD),
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.ACKR(ACKR),
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.ACOR(ACOR),
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.ACS(ACS),
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.AERR(AERR),
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.AI1(AI[0]),
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.AI10(AI[9]),
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.AI11(AI[10]),
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.AI12(AI[11]),
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.AI13(AI[12]),
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.AI14(AI[13]),
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.AI15(AI[14]),
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.AI16(AI[15]),
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.AI17(AI[16]),
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.AI18(AI[17]),
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.AI19(AI[18]),
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.AI2(AI[1]),
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.AI20(AI[19]),
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.AI21(AI[20]),
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.AI22(AI[21]),
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.AI23(AI[22]),
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.AI24(AI[23]),
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.AI3(AI[2]),
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.AI4(AI[3]),
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.AI5(AI[4]),
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.AI6(AI[5]),
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.AI7(AI[6]),
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.AI8(AI[7]),
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.AI9(AI[8]),
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.AO1(AO[0]),
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.AO10(AO[9]),
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.AO11(AO[10]),
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.AO12(AO[11]),
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.AO13(AO[12]),
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.AO14(AO[13]),
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.AO15(AO[14]),
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.AO16(AO[15]),
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.AO17(AO[16]),
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.AO18(AO[17]),
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.AO19(AO[18]),
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.AO2(AO[1]),
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.AO20(AO[19]),
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.AO21(AO[20]),
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.AO22(AO[21]),
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.AO23(AO[22]),
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.AO24(AO[23]),
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.AO3(AO[2]),
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.AO4(AO[3]),
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.AO5(AO[4]),
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.AO6(AO[5]),
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.AO7(AO[6]),
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.AO8(AO[7]),
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.AO9(AO[8]),
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.AR(AR),
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.AWE(AWE),
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.BA1(BA[0]),
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.BA10(BA[9]),
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.BA11(BA[10]),
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.BA12(BA[11]),
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.BA13(BA[12]),
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.BA14(BA[13]),
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.BA15(BA[14]),
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.BA16(BA[15]),
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.BA2(BA[1]),
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.BA3(BA[2]),
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.BA4(BA[3]),
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.BA5(BA[4]),
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.BA6(BA[5]),
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.BA7(BA[6]),
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.BA8(BA[7]),
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.BA9(BA[8]),
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.BCK(BCK),
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.BCKC(BCK),
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.BCKD(BCKD),
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.BCKR(BCKR),
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.BCOR(BCOR),
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.BCS(BCS),
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.BERR(BERR),
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.BI1(BI[0]),
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.BI10(BI[9]),
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.BI11(BI[10]),
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.BI12(BI[11]),
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.BI13(BI[12]),
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.BI14(BI[13]),
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.BI15(BI[14]),
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.BI16(BI[15]),
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.BI17(BI[16]),
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.BI18(BI[17]),
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.BI19(BI[18]),
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.BI2(BI[1]),
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.BI20(BI[19]),
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.BI21(BI[20]),
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.BI22(BI[21]),
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.BI23(BI[22]),
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.BI24(BI[23]),
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.BI3(BI[2]),
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.BI4(BI[3]),
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.BI5(BI[4]),
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.BI6(BI[5]),
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.BI7(BI[6]),
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.BI8(BI[7]),
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.BI9(BI[8]),
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.BO1(BO[0]),
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.BO10(BO[9]),
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.BO11(BO[10]),
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.BO12(BO[11]),
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.BO13(BO[12]),
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.BO14(BO[13]),
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.BO15(BO[14]),
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.BO16(BO[15]),
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.BO17(BO[16]),
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.BO18(BO[17]),
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.BO19(BO[18]),
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.BO2(BO[1]),
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.BO20(BO[19]),
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.BO21(BO[20]),
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.BO22(BO[21]),
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.BO23(BO[22]),
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.BO24(BO[23]),
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.BO3(BO[2]),
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.BO4(BO[3]),
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.BO5(BO[4]),
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.BO6(BO[5]),
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.BO7(BO[6]),
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.BO8(BO[7]),
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.BO9(BO[8]),
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.BR(BR),
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.BWE(BWE)
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);
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endmodule
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