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https://github.com/YosysHQ/yosys
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127 lines
2.9 KiB
Verilog
127 lines
2.9 KiB
Verilog
// NX_RAM related
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(* blackbox *)
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module NX_ECC(CKD, CHK, COR, ERR);
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input CHK;
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input CKD;
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output COR;
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output ERR;
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endmodule
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//TODO
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(* blackbox *)
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module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
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input [1:0] DS;
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input GS;
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output [2:0] GVDN;
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output [2:0] GVIN;
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output [2:0] GVON;
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input [5:0] LA;
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output [3:0] PA;
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endmodule
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//TODO
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(* blackbox *)
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module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
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input DCK;
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output [5:0] DID;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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input [4:0] I;
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output IO;
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input R;
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input SCK;
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parameter data_size = 5;
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parameter differential = "";
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parameter drive = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter outputCapacity = "";
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parameter outputDelayLine = "";
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parameter slewRate = "";
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parameter spath_dynamic = 1'b0;
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parameter standard = "";
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endmodule
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//TODO
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(* blackbox *)
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module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
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input DCK;
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output [5:0] DID;
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input DIG;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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output FLD;
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output FLG;
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input FZ;
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input IO;
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output [4:0] O;
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input R;
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input SCK;
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parameter data_size = 5;
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parameter differential = "";
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parameter dpath_dynamic = 1'b0;
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parameter drive = "";
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parameter inputDelayLine = "";
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parameter inputSignalSlope = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter standard = "";
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parameter termination = "";
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parameter terminationReference = "";
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parameter turbo = "";
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parameter weakTermination = "";
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endmodule
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//TODO
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(* blackbox *)
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module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
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, DID);
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input CCK;
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input CI;
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input CL;
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input CR;
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input DCK;
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output [5:0] DID;
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input DIG;
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input [5:0] DRA;
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input [5:0] DRI;
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input DRL;
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output [5:0] DRO;
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input [1:0] DS;
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input FCK;
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output FLD;
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output FLG;
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input FZ;
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input [4:0] I;
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inout IO;
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output [4:0] O;
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input RRX;
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input RTX;
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input SCK;
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parameter cpath_registered = 1'b0;
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parameter data_size = 5;
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parameter differential = "";
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parameter dpath_dynamic = 1'b0;
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parameter drive = "";
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parameter inputDelayLine = "";
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parameter inputSignalSlope = "";
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parameter location = "";
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parameter locked = 1'b0;
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parameter outputCapacity = "";
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parameter outputDelayLine = "";
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parameter slewRate = "";
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parameter spath_dynamic = 1'b0;
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parameter standard = "";
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parameter termination = "";
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parameter terminationReference = "";
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parameter turbo = "";
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parameter weakTermination = "";
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endmodule
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