mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-09 09:21:58 +00:00
759 lines
22 KiB
C++
759 lines
22 KiB
C++
#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include <tcl.h>
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#include <list>
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#include <optional>
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#include <iostream>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TclCall {
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Tcl_Interp *interp;
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int objc;
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Tcl_Obj* const* objv;
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};
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static int redirect_unknown(TclCall call);
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static size_t get_node_count(Tcl_Interp* interp);
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struct BitSelection {
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bool all = false;
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std::vector<bool> bits = {};
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void set_all() {
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bits.clear();
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all = true;
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}
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void clear() {
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bits.clear();
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all = false;
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}
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void set(size_t idx) {
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if (all)
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return;
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if (idx >= bits.size())
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bits.resize(idx + 1);
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bits[idx] = true;
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}
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void merge(const BitSelection& other) {
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if (all)
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return;
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if (other.all) {
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set_all();
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return;
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}
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if (other.bits.size() > bits.size())
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bits.resize(other.bits.size());
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for (size_t other_idx = 0; other_idx < other.bits.size(); other_idx++) {
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bool other_bit = other.bits[other_idx];
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if (other_bit)
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set(other_idx);
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}
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}
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void dump() {
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if (!all) {
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for (size_t i = 0; i < bits.size(); i++)
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if (bits[i])
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log("\t\t [%zu]\n", i);
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} else {
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log("\t\t FULL\n");
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}
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}
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bool is_set(size_t idx) const {
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if (all)
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return true;
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if (idx >= bits.size())
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return false;
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return bits[idx];
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}
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// TODO actually use this
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void compress(size_t size) {
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if (bits.size() < size)
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return;
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for (size_t i = 0; i < size; i++)
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if (!bits[i])
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return;
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bits.clear();
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bits.shrink_to_fit();
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all = true;
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}
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};
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struct SdcObjects {
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enum CollectMode {
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// getter-side object tracking with minimal features
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SimpleGetter,
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// getter-side object tracking with everything
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FullGetter,
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// constraint-side tracking
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FullConstraint,
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} collect_mode;
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using CellPin = std::pair<Cell*, IdString>;
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Design* design;
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std::vector<std::pair<std::string, Wire*>> design_ports;
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std::vector<std::pair<std::string, Cell*>> design_cells;
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std::vector<std::pair<std::string, CellPin>> design_pins;
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std::vector<std::pair<std::string, Wire*>> design_nets;
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using PortPattern = std::tuple<std::string, Wire*, BitSelection>;
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using PinPattern = std::tuple<std::string, SdcObjects::CellPin, BitSelection>;
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std::vector<std::vector<PortPattern>> resolved_port_pattern_sets;
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std::vector<std::vector<PinPattern>> resolved_pin_pattern_sets;
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// TODO
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dict<std::pair<std::string, Wire*>, BitSelection> constrained_ports;
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pool<std::pair<std::string, Cell*>> constrained_cells;
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dict<std::pair<std::string, CellPin>, BitSelection> constrained_pins;
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dict<std::pair<std::string, Wire*>, BitSelection> constrained_nets;
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void sniff_module(std::list<std::string>& hierarchy, Module* mod) {
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std::string prefix;
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for (auto mod_name : hierarchy) {
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if (prefix.length())
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prefix += "/"; // TODO seperator?
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prefix += mod_name;
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}
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for (auto* wire : mod->wires()) {
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std::string name = wire->name.str();
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log_assert(name.length());
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// TODO: really skip internal wires?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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design_nets.push_back(std::make_pair(path, wire));
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}
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for (auto* cell : mod->cells()) {
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std::string name = cell->name.str();
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// TODO: really skip internal cells?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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design_cells.push_back(std::make_pair(path, cell));
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for (auto pin : cell->connections()) {
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IdString pin_name = pin.first;
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std::string pin_name_sdc = path + "/" + pin.first.str().substr(1);
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design_pins.push_back(std::make_pair(pin_name_sdc, std::make_pair(cell, pin_name)));
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}
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if (auto sub_mod = mod->design->module(cell->type)) {
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hierarchy.push_back(name);
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sniff_module(hierarchy, sub_mod);
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hierarchy.pop_back();
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}
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}
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}
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SdcObjects(Design* design) : design(design) {
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Module* top = design->top_module();
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if (!top)
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log_error("Top module couldn't be determined. Check 'top' attribute usage");
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for (auto port : top->ports) {
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design_ports.push_back(std::make_pair(port.str().substr(1), top->wire(port)));
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}
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std::list<std::string> hierarchy{};
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sniff_module(hierarchy, top);
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}
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~SdcObjects() = default;
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template <typename T, typename U>
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void build_normal_result(Tcl_Interp* interp, std::vector<std::tuple<std::string, T, BitSelection>>&& resolved, U& tgt, std::function<size_t(T&)> width, Tcl_Obj*& result) {
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if (!result)
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result = Tcl_NewListObj(resolved.size(), nullptr);
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for (auto [name, obj, matching_bits] : resolved) {
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for (size_t i = 0; i < width(obj); i++)
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if (matching_bits.is_set(i)) {
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Tcl_ListObjAppendElement(interp, result, Tcl_NewStringObj(name.c_str(), name.size()));
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break;
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}
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}
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size_t node_count = get_node_count(interp);
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tgt.emplace_back(std::move(resolved));
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log("%zu %zu\n", node_count, tgt.size());
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log_assert(node_count == tgt.size());
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}
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template <typename T>
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void merge_as_constrained(std::vector<std::tuple<std::string, T, BitSelection>>&& resolved) {
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for (auto [name, obj, matching_bits] : resolved) {
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merge_or_init(std::make_pair(name, obj), constrained_pins, matching_bits);
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}
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}
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void dump() {
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std::sort(design_ports.begin(), design_ports.end());
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std::sort(design_cells.begin(), design_cells.end());
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std::sort(design_pins.begin(), design_pins.end());
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std::sort(design_nets.begin(), design_nets.end());
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constrained_ports.sort();
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constrained_cells.sort();
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constrained_pins.sort();
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constrained_nets.sort();
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// log("Design ports:\n");
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// for (auto name : design_ports) {
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// log("\t%s\n", name.c_str());
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// }
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// log("Design cells:\n");
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// for (auto [name, cell] : design_cells) {
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// (void)cell;
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// log("\t%s\n", name.c_str());
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// }
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// log("Design pins:\n");
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// for (auto [name, pin] : design_pins) {
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// (void)pin;
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// log("\t%s\n", name.c_str());
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// }
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// log("Design nets:\n");
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// for (auto [name, net] : design_nets) {
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// (void)net;
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// log("\t%s\n", name.c_str());
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// }
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// log("\n");
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log("Constrained ports:\n");
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for (auto [ref, bits] : constrained_ports) {
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auto [name, port] = ref;
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(void)port;
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log("\t%s\n", name.c_str());
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bits.dump();
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}
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log("Constrained cells:\n");
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for (auto& [name, cell] : constrained_cells) {
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(void)cell;
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log("\t%s\n", name.c_str());
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}
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log("Constrained pins:\n");
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for (auto& [ref, bits] : constrained_pins) {
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auto [name, pin] = ref;
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(void)pin;
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log("\t%s\n", name.c_str());
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bits.dump();
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}
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log("Constrained nets:\n");
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for (auto& [ref, bits] : constrained_nets) {
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auto [name, net] = ref;
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(void)net;
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log("\t%s\n", name.c_str());
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bits.dump();
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}
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log("\n");
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}
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class KeepHierarchyWorker {
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std::unordered_set<Module*> tracked_modules = {};
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Design* design = nullptr;
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bool mark(Module* mod) {
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for (auto* cell : mod->cells()) {
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if (auto* submod = design->module(cell->type))
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if (mark(submod)) {
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mod->set_bool_attribute(ID::keep_hierarchy);
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return true;
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}
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}
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if (tracked_modules.count(mod)) {
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mod->set_bool_attribute(ID::keep_hierarchy);
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return true;
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}
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return false;
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}
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public:
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KeepHierarchyWorker(SdcObjects* objects, Design* d) : design(d) {
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for (auto [ref, _] : objects->constrained_ports) {
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tracked_modules.insert(ref.second->module);
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}
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for (auto& [_, cell] : objects->constrained_cells) {
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tracked_modules.insert(cell->module);
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}
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for (auto& [ref, _] : objects->constrained_pins) {
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tracked_modules.insert(ref.second.first->module);
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}
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for (auto& [ref, _] : objects->constrained_nets) {
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tracked_modules.insert(ref.second->module);
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}
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log_debug("keep_hierarchy tracked modules:\n");
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for (auto* mod : tracked_modules)
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log_debug("\t%s\n", mod->name);
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}
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bool mark() {
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return mark(design->top_module());
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}
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};
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void keep_hierarchy() {
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(void)KeepHierarchyWorker(this, design).mark();
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}
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};
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// TODO vectors
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// TODO cell arrays?
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struct MatchConfig {
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enum MatchMode {
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WILDCARD,
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REGEX,
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} match;
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bool match_case;
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enum HierMode {
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FLAT,
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TREE,
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} hier;
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MatchConfig(bool regexp_flag, bool nocase_flag, bool hierarchical_flag) :
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match(regexp_flag ? REGEX : WILDCARD),
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match_case(!nocase_flag),
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hier(hierarchical_flag ? FLAT : TREE) { }
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};
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static std::pair<bool, BitSelection> matches(std::string name, const std::string& pat, const MatchConfig& config) {
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(void)config;
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bool got_bit_index = false;;
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int bit_idx;
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std::string pat_base = pat;
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size_t pos = pat.rfind('[');
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if (pos != std::string::npos) {
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got_bit_index = true;
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pat_base = pat.substr(0, pos);
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std::string bit_selector = pat.substr(pos + 1, pat.rfind(']') - pos - 1);
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for (auto c : bit_selector)
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if (!std::isdigit(c))
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log_error("Unsupported bit selector %s in SDC pattern %s\n",
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bit_selector.c_str(), pat.c_str());
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bit_idx = std::stoi(bit_selector);
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}
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BitSelection bits = {};
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if (name == pat_base) {
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if (got_bit_index) {
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bits.set(bit_idx);
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return std::make_pair(true, bits);
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} else {
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bits.set_all();
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return std::make_pair(true, bits);
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}
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} else {
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return std::make_pair(false, bits);
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}
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}
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static int graph_node(TclCall call) {
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// TODO is that it?
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return redirect_unknown(call);
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}
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static int redirect_unknown(TclCall call) {
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// TODO redirect to different command
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Tcl_Obj *newCmd = Tcl_NewStringObj("unknown", -1);
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auto newObjc = call.objc + 1;
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Tcl_Obj **newObjv = new Tcl_Obj*[newObjc];
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newObjv[0] = newCmd;
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for (int i = 1; i < newObjc; i++) {
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newObjv[i] = call.objv[i - 1];
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}
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int result = Tcl_EvalObjv(call.interp, newObjc, newObjv, 0);
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Tcl_DecrRefCount(newCmd);
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delete[] newObjv;
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return result;
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}
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struct SdcGraphNode {
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using Child = std::variant<SdcGraphNode*, std::string>;
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std::vector<Child> children;
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SdcGraphNode() = default;
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void addChild(SdcGraphNode* child) {
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children.push_back(child);
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}
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void addChild(std::string tcl_string) {
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children.push_back(tcl_string);
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}
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void dump(std::ostream& os) const {
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bool first = true;
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for (auto child : children) {
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if (first) {
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first = false;
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} else {
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os << " ";
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}
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if (auto* s = std::get_if<std::string>(&child))
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os << *s;
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else if (SdcGraphNode*& c = *std::get_if<SdcGraphNode*>(&child)) {
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os << "[";
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c->dump(os);
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os << "]";
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} else {
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log_assert(false);
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}
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}
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}
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};
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static size_t get_node_count(Tcl_Interp* interp) {
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const char* idx_raw = Tcl_GetVar(interp, "sdc_call_index", TCL_GLOBAL_ONLY);
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log_assert(idx_raw);
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std::string idx(idx_raw);
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for (auto c : idx)
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if (!std::isdigit(c))
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log_error("sdc_call_index non-numeric value %s\n", idx.c_str());
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return std::stoi(idx);
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}
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std::vector<std::vector<std::string>> gather_nested_calls(Tcl_Interp* interp) {
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Tcl_Obj* listObj = Tcl_GetVar2Ex(interp, "sdc_calls", nullptr, TCL_GLOBAL_ONLY);
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int listLength;
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std::vector<std::vector<std::string>> sdc_calls;
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if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
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for (int i = 0; i < listLength; i++) {
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Tcl_Obj* subListObj;
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std::vector<std::string> subList;
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if (Tcl_ListObjIndex(interp, listObj, i, &subListObj) != TCL_OK) {
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log_error("broken list of lists\n");
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}
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int subListLength;
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if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
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// Valid list - extract elements
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for (int j = 0; j < subListLength; j++) {
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Tcl_Obj* elementObj;
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if (Tcl_ListObjIndex(interp, subListObj, j, &elementObj) == TCL_OK) {
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const char* elementStr = Tcl_GetString(elementObj);
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subList.push_back(std::string(elementStr));
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}
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}
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} else {
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// Single element, not a list
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const char* elementStr = Tcl_GetString(subListObj);
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subList.push_back(std::string(elementStr));
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}
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sdc_calls.push_back(subList);
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}
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}
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log_assert(sdc_calls.size() == get_node_count(interp));
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return sdc_calls;
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}
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std::vector<SdcGraphNode> build_graph(const std::vector<std::vector<std::string>>& sdc_calls) {
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size_t node_count = sdc_calls.size();
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std::vector<SdcGraphNode> graph(node_count);
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for (size_t i = 0; i < node_count; i++) {
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auto& new_node = graph[i];
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for (size_t j = 0; j < sdc_calls[i].size(); j++) {
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auto arg = sdc_calls[i][j];
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const std::string prefix = "YOSYS_SDC_MAGIC_NODE_";
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auto pos = arg.find(prefix);
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if (pos != std::string::npos) {
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std::string rest = arg.substr(pos + prefix.length());
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for (auto c : rest)
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if (!std::isdigit(c))
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log_error("weird thing %s in %s\n", rest.c_str(), arg.c_str());
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size_t arg_node_idx = std::stoi(rest);
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log_assert(arg_node_idx < graph.size());
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new_node.addChild(&graph[arg_node_idx]);
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} else {
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new_node.addChild(arg);
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}
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}
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}
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return graph;
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}
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std::vector<bool> node_ownership(const std::vector<SdcGraphNode>& graph) {
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std::vector<bool> has_parent(graph.size());
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for (auto node : graph) {
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for (auto child : node.children) {
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if (SdcGraphNode** pp = std::get_if<SdcGraphNode*>(&child)) {
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size_t idx = std::distance(&graph.front(), (const SdcGraphNode*)*pp);
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log_assert(idx < has_parent.size());
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has_parent[idx] = true;
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}
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}
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}
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return has_parent;
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}
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void dump_sdc_graph(const std::vector<SdcGraphNode>& graph, const std::vector<bool>& has_parent) {
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for (size_t i = 0; i < graph.size(); i++) {
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if (!has_parent[i]) {
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graph[i].dump(std::cout);
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std::cout << "\n";
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}
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}
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}
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void inspect_globals(Tcl_Interp* interp, bool dump_mode) {
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std::vector<std::vector<std::string>> sdc_calls = gather_nested_calls(interp);
|
|
std::vector<SdcGraphNode> graph = build_graph(sdc_calls);
|
|
if (dump_mode)
|
|
dump_sdc_graph(graph, node_ownership(graph));
|
|
}
|
|
|
|
// patterns -> (pattern-object-bit)s
|
|
template <typename T, typename U>
|
|
std::vector<std::tuple<std::string, T, BitSelection>>
|
|
find_matching(U objects, const MatchConfig& config, const std::vector<std::string> &patterns, const char* obj_type)
|
|
{
|
|
std::vector<std::tuple<std::string, T, BitSelection>> resolved;
|
|
for (auto pat : patterns) {
|
|
bool found = false;
|
|
for (auto [name, obj] : objects) {
|
|
auto [does_match, matching_bits] = matches(name, pat, config);
|
|
if (does_match) {
|
|
found = true;
|
|
resolved.push_back(std::make_tuple(name, obj, matching_bits));
|
|
// TODO add a continue statement, conditional on config
|
|
}
|
|
}
|
|
if (!found)
|
|
log_warning("No matches in design for %s %s\n", obj_type, pat.c_str());
|
|
}
|
|
return resolved;
|
|
}
|
|
|
|
struct TclOpts {
|
|
const char* name;
|
|
std::initializer_list<const char*> legals;
|
|
TclOpts(const char* name, std::initializer_list<const char*> legals) : name(name), legals(legals) {}
|
|
bool parse_opt(Tcl_Obj* obj, const char* opt_name) {
|
|
char* arg = Tcl_GetString(obj);
|
|
std::string expected = std::string("-") + opt_name;
|
|
if (expected == arg) {
|
|
if (!std::find_if(legals.begin(), legals.end(),
|
|
[&opt_name](const char* str) { return opt_name == str; }))
|
|
log_cmd_error("Illegal argument %s for %s.\n", expected.c_str(), name);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
};
|
|
|
|
struct GetterOpts : TclOpts {
|
|
bool hierarchical_flag = false;
|
|
bool regexp_flag = false;
|
|
bool nocase_flag = false;
|
|
std::string separator = "/";
|
|
Tcl_Obj* of_objects = nullptr;
|
|
std::vector<std::string> patterns = {};
|
|
GetterOpts(const char* name, std::initializer_list<const char*> legals) : TclOpts(name, legals) {}
|
|
template<typename T>
|
|
bool parse_flag(Tcl_Obj* obj, const char* flag_name, T& flag_var) {
|
|
bool ret = parse_opt(obj, flag_name);
|
|
if (ret)
|
|
flag_var = true;
|
|
return ret;
|
|
}
|
|
void parse(int objc, Tcl_Obj* const objv[]) {
|
|
int i = 1;
|
|
for (; i < objc; i++) {
|
|
if (parse_flag(objv[i], "hierarchical", hierarchical_flag)) continue;
|
|
if (parse_flag(objv[i], "hier", hierarchical_flag)) continue;
|
|
if (parse_flag(objv[i], "regexp", regexp_flag)) continue;
|
|
if (parse_flag(objv[i], "nocase", nocase_flag)) continue;
|
|
if (parse_opt(objv[i], "hsc")) {
|
|
log_assert(i + 1 < objc);
|
|
separator = Tcl_GetString(objv[++i]);
|
|
continue;
|
|
}
|
|
if (parse_opt(objv[i], "of_objects")) {
|
|
log_assert(i + 1 < objc);
|
|
of_objects = objv[++i];
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
for (; i < objc; i++) {
|
|
patterns.push_back(Tcl_GetString(objv[i]));
|
|
}
|
|
};
|
|
void check_simple() {
|
|
if (regexp_flag || hierarchical_flag || nocase_flag || separator != "/" || of_objects) {
|
|
log_error("%s got unexpected flags in simple mode\n", name);
|
|
}
|
|
if (patterns.size() != 1)
|
|
log_error("%s got unexpected number of patterns in simple mode: %zu\n", name, patterns.size());
|
|
}
|
|
void check_simple_sep() {
|
|
if (separator != "/")
|
|
log_error("Only '/' accepted as separator");
|
|
}
|
|
};
|
|
|
|
template <typename T>
|
|
void merge_or_init(const T& key, dict<T, BitSelection>& dst, const BitSelection& src) {
|
|
if (dst.count(key) == 0) {
|
|
dst[key] = src;
|
|
} else {
|
|
dst[key].merge(src);
|
|
}
|
|
}
|
|
|
|
static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
|
|
{
|
|
auto* objects = (SdcObjects*)data;
|
|
GetterOpts opts("get_pins", {"hierarchical", "hier", "regexp", "nocase", "hsc", "of_objects"});
|
|
opts.parse(objc, objv);
|
|
if (objects->collect_mode == SdcObjects::CollectMode::SimpleGetter)
|
|
opts.check_simple();
|
|
opts.check_simple_sep();
|
|
|
|
MatchConfig config(opts.regexp_flag, opts.nocase_flag, opts.hierarchical_flag);
|
|
std::vector<std::tuple<std::string, SdcObjects::CellPin, BitSelection>> resolved;
|
|
const auto& pins = objects->design_pins;
|
|
resolved = find_matching<SdcObjects::CellPin, decltype(pins)>(pins, config, opts.patterns, "pin");
|
|
|
|
return graph_node(TclCall{interp, objc, objv});
|
|
}
|
|
|
|
static int sdc_get_ports_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
|
|
{
|
|
auto* objects = (SdcObjects*)data;
|
|
GetterOpts opts("get_ports", {"regexp", "nocase"});
|
|
opts.parse(objc, objv);
|
|
if (objects->collect_mode == SdcObjects::CollectMode::SimpleGetter)
|
|
opts.check_simple();
|
|
|
|
MatchConfig config(opts.regexp_flag, opts.nocase_flag, false);
|
|
std::vector<std::tuple<std::string, Wire*, BitSelection>> resolved;
|
|
const auto& ports = objects->design_ports;
|
|
resolved = find_matching<Wire*, decltype(ports)>(ports, config, opts.patterns, "port");
|
|
|
|
for (auto [name, wire, matching_bits] : resolved) {
|
|
if (objects->collect_mode != SdcObjects::CollectMode::FullConstraint)
|
|
merge_or_init(std::make_pair(name, wire), objects->constrained_ports, matching_bits);
|
|
}
|
|
|
|
return graph_node(TclCall{interp, objc, objv});
|
|
}
|
|
|
|
static int sdc_get_nets_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
|
|
{
|
|
auto* objects = (SdcObjects*)data;
|
|
GetterOpts opts("get_nets", {"hierarchical", "hier", "regexp", "nocase", "hsc", "of_objects"});
|
|
opts.parse(objc, objv);
|
|
if (objects->collect_mode == SdcObjects::CollectMode::SimpleGetter)
|
|
opts.check_simple();
|
|
|
|
MatchConfig config(opts.regexp_flag, opts.nocase_flag, false);
|
|
std::vector<std::tuple<std::string, Wire*, BitSelection>> resolved;
|
|
const auto& ports = objects->design_nets;
|
|
resolved = find_matching<Wire*, decltype(ports)>(ports, config, opts.patterns, "net");
|
|
|
|
for (auto [name, wire, matching_bits] : resolved) {
|
|
if (objects->collect_mode != SdcObjects::CollectMode::FullConstraint)
|
|
merge_or_init(std::make_pair(name, wire), objects->constrained_nets, matching_bits);
|
|
}
|
|
|
|
return graph_node(TclCall{interp, objc, objv});
|
|
}
|
|
|
|
class SDCInterpreter
|
|
{
|
|
private:
|
|
Tcl_Interp* interp = nullptr;
|
|
public:
|
|
std::unique_ptr<SdcObjects> objects;
|
|
~SDCInterpreter() {
|
|
if (interp)
|
|
Tcl_DeleteInterp(interp);
|
|
}
|
|
static SDCInterpreter& get() {
|
|
static SDCInterpreter instance;
|
|
return instance;
|
|
}
|
|
Tcl_Interp* fresh_interp(Design* design) {
|
|
if (interp)
|
|
Tcl_DeleteInterp(interp);
|
|
|
|
interp = Tcl_CreateInterp();
|
|
if (Tcl_Init(interp)!=TCL_OK)
|
|
log_error("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno()));
|
|
|
|
objects = std::make_unique<SdcObjects>(design);
|
|
objects->collect_mode = SdcObjects::CollectMode::SimpleGetter;
|
|
Tcl_CreateObjCommand(interp, "get_pins", sdc_get_pins_cmd, (ClientData) objects.get(), NULL);
|
|
Tcl_CreateObjCommand(interp, "get_nets", sdc_get_nets_cmd, (ClientData) objects.get(), NULL);
|
|
Tcl_CreateObjCommand(interp, "get_ports", sdc_get_ports_cmd, (ClientData) objects.get(), NULL);
|
|
return interp;
|
|
}
|
|
};
|
|
|
|
// Also see TclPass
|
|
struct SdcPass : public Pass {
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" sdc [options] file\n");
|
|
log("\n");
|
|
log("Read the SDC file for the current design.\n");
|
|
log("\n");
|
|
log(" -dump\n");
|
|
log(" Dump the referenced design objects.\n");
|
|
log("\n");
|
|
log(" -dump-graph\n");
|
|
log(" Dump the uninterpreted call graph.\n");
|
|
log("\n");
|
|
log(" -keep_hierarchy\n");
|
|
log(" Add keep_hierarchy attributes while retaining SDC validity.\n");
|
|
log("\n");
|
|
}
|
|
SdcPass() : Pass("sdc", "sniff at some SDC") { }
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
|
|
log_header(design, "Executing SDC pass.\n");
|
|
log_experimental("sdc");
|
|
size_t argidx;
|
|
bool dump_mode = false;
|
|
bool dump_graph_mode = false;
|
|
bool keep_hierarchy_mode = false;
|
|
std::vector<std::string> stubs_paths;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-dump") {
|
|
dump_mode = true;
|
|
continue;
|
|
} else if (args[argidx] == "-dump-graph") {
|
|
dump_graph_mode = true;
|
|
continue;
|
|
} else if (args[argidx] == "-keep_hierarchy") {
|
|
keep_hierarchy_mode = true;
|
|
continue;
|
|
} else if (args[argidx] == "-stubs" && argidx+1 < args.size()) {
|
|
stubs_paths.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
if (argidx >= args.size())
|
|
log_cmd_error("Missing SDC file.\n");
|
|
|
|
std::string sdc_path = args[argidx++];
|
|
if (argidx < args.size())
|
|
log_cmd_error("Unexpected extra positional argument %s after SDC file %s.\n", args[argidx], sdc_path);
|
|
SDCInterpreter& sdc = SDCInterpreter::get();
|
|
Tcl_Interp *interp = sdc.fresh_interp(design);
|
|
Tcl_Preserve(interp);
|
|
std::string stub_path = "+/sdc/graph-stubs.sdc";
|
|
rewrite_filename(stub_path);
|
|
if (Tcl_EvalFile(interp, stub_path.c_str()) != TCL_OK)
|
|
log_cmd_error("SDC interpreter returned an error in stub preamble file: %s\n", Tcl_GetStringResult(interp));
|
|
for (auto path : stubs_paths)
|
|
if (Tcl_EvalFile(interp, path.c_str()) != TCL_OK)
|
|
log_cmd_error("SDC interpreter returned an error in OpenSTA stub file %s: %s\n", path.c_str(), Tcl_GetStringResult(interp));
|
|
if (Tcl_EvalFile(interp, sdc_path.c_str()) != TCL_OK)
|
|
log_cmd_error("SDC interpreter returned an error: %s\n", Tcl_GetStringResult(interp));
|
|
if (dump_mode)
|
|
sdc.objects->dump();
|
|
if (keep_hierarchy_mode)
|
|
sdc.objects->keep_hierarchy();
|
|
inspect_globals(interp, dump_graph_mode);
|
|
Tcl_Release(interp);
|
|
}
|
|
} SdcPass;
|
|
|
|
YOSYS_NAMESPACE_END
|