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657 lines
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ReStructuredText
657 lines
27 KiB
ReStructuredText
.. _chapter:verilog:
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The Verilog and AST frontends
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=============================
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This chapter provides an overview of the implementation of the Yosys Verilog and
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AST frontends. The Verilog frontend reads Verilog-2005 code and creates an
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abstract syntax tree (AST) representation of the input. This AST representation
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is then passed to the AST frontend that converts it to RTLIL data, as
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illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
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.. figure:: /_images/internals/verilog_flow.*
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:class: width-helper invert-helper
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:name: fig:Verilog_flow
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Simplified Verilog to RTLIL data flow
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Transforming Verilog to AST
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---------------------------
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The Verilog frontend converts the Verilog sources to an internal AST
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representation that closely resembles the structure of the original Verilog
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code. The Verilog frontend consists of three components, the Preprocessor, the
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Lexer and the Parser.
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The source code to the Verilog frontend can be found in
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:file:`frontends/verilog/` in the Yosys source tree.
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The Verilog preprocessor
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~~~~~~~~~~~~~~~~~~~~~~~~
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The Verilog preprocessor scans over the Verilog source code and interprets some
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of the Verilog compiler directives such as :literal:`\`include`,
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:literal:`\`define` and :literal:`\`ifdef`.
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It is implemented as a C++ function that is passed a file descriptor as input
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and returns the pre-processed Verilog code as a ``std::string``.
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The source code to the Verilog Preprocessor can be found in
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:file:`frontends/verilog/preproc.cc` in the Yosys source tree.
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The Verilog lexer
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~~~~~~~~~~~~~~~~~
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The Verilog Lexer is written using the lexer generator flex. Its source code can
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be found in :file:`frontends/verilog/verilog_lexer.l` in the Yosys source tree.
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The lexer does little more than identifying all keywords and literals recognised
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by the Yosys Verilog frontend.
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The lexer keeps track of the current location in the Verilog source code with
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a ``VerilogLexer::out_loc`` and uses it to construct parser-defined
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symbol objects.
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Finally the lexer identifies and handles special comments such as "``// synopsys
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translate_off``" and "``// synopsys full_case``". (It is recommended to use
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:literal:`\`ifdef` constructs instead of the Synsopsys translate_on/off comments
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and attributes such as ``(* full_case *)`` over "``// synopsys full_case``"
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whenever possible.)
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The Verilog parser
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~~~~~~~~~~~~~~~~~~
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The Verilog Parser is written using the parser generator bison. Its source code
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can be found in :file:`frontends/verilog/verilog_parser.y` in the Yosys source
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tree.
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It generates an AST using the ``AST::AstNode`` data structure defined in
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:file:`frontends/ast/ast.h`. An ``AST::AstNode`` object has the following
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properties:
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.. list-table:: AST node types with their corresponding Verilog constructs.
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:name: tab:Verilog_AstNodeType
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:widths: 50 50
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* - AST Node Type
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- Corresponding Verilog Construct
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* - AST_NONE
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- This Node type should never be used.
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* - AST_DESIGN
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- This node type is used for the top node of the AST tree. It has no
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corresponding Verilog construct.
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* - AST_MODULE, AST_TASK, AST_FUNCTION
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- ``module``, ``task`` and ``function``
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* - AST_WIRE
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- ``input``, ``output``, ``wire``, ``reg`` and ``integer``
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* - AST_MEMORY
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- Verilog Arrays
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* - AST_AUTOWIRE
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- Created by the simplifier when an undeclared signal name is used.
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* - AST_PARAMETER, AST_LOCALPARAM
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- ``parameter`` and ``localparam``
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* - AST_PARASET
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- Parameter set in cell instantiation
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* - AST_ARGUMENT
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- Port connection in cell instantiation
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* - AST_RANGE
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- Bit-Index in a signal or element index in array
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* - AST_CONSTANT
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- A literal value
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* - AST_CELLTYPE
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- The type of cell in cell instantiation
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* - AST_IDENTIFIER
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- An Identifier (signal name in expression or cell/task/etc. name in other
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contexts)
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* - AST_PREFIX
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- Construct an identifier in the form <prefix>[<index>].<suffix> (used
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only in advanced generate constructs)
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* - AST_FCALL, AST_TCALL
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- Call to function or task
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* - AST_TO_SIGNED, AST_TO_UNSIGNED
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- The ``$signed()`` and ``$unsigned()`` functions
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* - AST_CONCAT, AST_REPLICATE
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- The ``{...}`` and ``{...{...}}`` operators
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* - AST_BIT_NOT, AST_BIT_AND, AST_BIT_OR, AST_BIT_XOR, AST_BIT_XNOR
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- The bitwise operators ``~``, ``&``, ``|``, ``^`` and ``~^``
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* - AST_REDUCE_AND, AST_REDUCE_OR, AST_REDUCE_XOR, AST_REDUCE_XNOR
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- The unary reduction operators ``~``, ``&``, ``|``, ``^`` and ``~^``
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* - AST_REDUCE_BOOL
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- Conversion from multi-bit value to boolean value (equivalent to
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AST_REDUCE_OR)
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* - AST_SHIFT_LEFT, AST_SHIFT_RIGHT, AST_SHIFT_SLEFT, AST_SHIFT_SRIGHT
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- The shift operators ``<<``, ``>>``, ``<<<`` and ``>>>``
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* - AST_LT, AST_LE, AST_EQ, AST_NE, AST_GE, AST_GT
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- The relational operators ``<``, ``<=``, ``==``, ``!=``, ``>=`` and ``>``
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* - AST_ADD, AST_SUB, AST_MUL, AST_DIV, AST_MOD, AST_POW
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- The binary operators ``+``, ``-``, ``*``, ``/``, ``%`` and ``**``
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* - AST_POS, AST_NEG
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- The prefix operators ``+`` and ``-``
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* - AST_LOGIC_AND, AST_LOGIC_OR, AST_LOGIC_NOT
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- The logic operators ``&&``, ``||`` and ``!``
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* - AST_TERNARY
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- The ternary ``?:``-operator
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* - AST_MEMRD AST_MEMWR
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- Read and write memories. These nodes are generated by the AST simplifier
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for writes/reads to/from Verilog arrays.
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* - AST_ASSIGN
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- An ``assign`` statement
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* - AST_CELL
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- A cell instantiation
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* - AST_PRIMITIVE
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- A primitive cell (``and``, ``nand``, ``or``, etc.)
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* - AST_ALWAYS, AST_INITIAL
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- Verilog ``always``- and ``initial``-blocks
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* - AST_BLOCK
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- A ``begin``-``end``-block
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* - AST_ASSIGN_EQ. AST_ASSIGN_LE
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- Blocking (``=``) and nonblocking (``<=``) assignments within an
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``always``- or ``initial``-block
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* - AST_CASE. AST_COND, AST_DEFAULT
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- The ``case`` (``if``) statements, conditions within a case and the
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default case respectively
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* - AST_FOR
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- A ``for``-loop with an ``always``- or ``initial``-block
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* - AST_GENVAR, AST_GENBLOCK, AST_GENFOR, AST_GENIF
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- The ``genvar`` and ``generate`` keywords and ``for`` and ``if`` within a
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generate block.
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* - AST_POSEDGE, AST_NEGEDGE, AST_EDGE
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- Event conditions for ``always`` blocks.
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- | The node type
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| This enum (``AST::AstNodeType``) specifies the role of the node.
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:numref:`Table %s <tab:Verilog_AstNodeType>` contains a list of all node
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types.
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- | The child nodes
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| This is a list of pointers to all children in the abstract syntax tree.
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- | Attributes
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| As almost every AST node might have Verilog attributes assigned to it, the
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``AST::AstNode`` has direct support for attributes. Note that the attribute
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values are again AST nodes.
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- | Node content
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| Each node might have additional content data. A series of member variables
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exist to hold such data. For example the member ``std::string str`` can
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hold a string value and is used e.g. in the ``AST_IDENTIFIER`` node type to
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store the identifier name.
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- | Source code location
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| Each ``AST::AstNode`` is automatically annotated with the current source
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code location by the ``AST::AstNode`` constructor. The ``location`` type
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is a manual reimplementation of the bison-provided location type. This
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type is defined at ``frontends/verilog/verilog_location.h``.
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The ``AST::AstNode`` constructor can be called with up to 4 child nodes. This
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simplifies the creation of AST nodes for simple expressions a bit. For example
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the bison code for parsing multiplications:
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.. code:: none
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:number-lines:
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basic_expr TOK_ASTER attr basic_expr {
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$$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4));
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SET_AST_NODE_LOC($$.get(), @1, @4);
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append_attr($$.get(), $3);
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} |
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The generated AST data structure is then passed directly to the AST frontend
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that performs the actual conversion to RTLIL.
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Note that the Yosys command ``read_verilog`` provides the options ``-yydebug``
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and ``-dump_ast`` that can be used to print the parse tree or abstract syntax
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tree respectively.
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Transforming AST to RTLIL
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-------------------------
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The AST frontend converts a set of modules in AST representation to modules in
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RTLIL representation and adds them to the current design. This is done in two
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steps: simplification and RTLIL generation.
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The source code to the AST frontend can be found in ``frontends/ast/`` in the
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Yosys source tree.
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AST simplification
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~~~~~~~~~~~~~~~~~~
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A full-featured AST is too complex to be transformed into RTLIL directly.
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Therefore it must first be brought into a simpler form. This is done by calling
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the ``AST::AstNode::simplify()`` method of all ``AST_MODULE`` nodes in the AST.
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This initiates a recursive process that performs the following transformations
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on the AST data structure:
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- Inline all task and function calls.
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- Evaluate all ``generate``-statements and unroll all ``for``-loops.
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- Perform const folding where it is necessary (e.g. in the value part of
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``AST_PARAMETER``, ``AST_LOCALPARAM``, ``AST_PARASET`` and ``AST_RANGE``
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nodes).
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- Replace ``AST_PRIMITIVE`` nodes with appropriate ``AST_ASSIGN`` nodes.
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- Replace dynamic bit ranges in the left-hand-side of assignments with
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``AST_CASE`` nodes with ``AST_COND`` children for each possible case.
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- Detect array access patterns that are too complicated for the
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``RTLIL::Memory`` abstraction and replace them with a set of signals and
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cases for all reads and/or writes.
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- Otherwise replace array accesses with ``AST_MEMRD`` and ``AST_MEMWR`` nodes.
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In addition to these transformations, the simplifier also annotates the
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AST with additional information that is needed for the RTLIL generator,
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namely:
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- All ranges (width of signals and bit selections) are not only const
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folded but (when a constant value is found) are also written to
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member variables in the AST_RANGE node.
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- All identifiers are resolved and all ``AST_IDENTIFIER`` nodes are annotated
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with a pointer to the AST node that contains the declaration of the
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identifier. If no declaration has been found, an ``AST_AUTOWIRE`` node is
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created and used for the annotation.
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This produces an AST that is fairly easy to convert to the RTLIL format.
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Generating RTLIL
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~~~~~~~~~~~~~~~~
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After AST simplification, the ``AST::AstNode::genRTLIL()`` method of each
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``AST_MODULE`` node in the AST is called. This initiates a recursive process
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that generates equivalent RTLIL data for the AST data.
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The ``AST::AstNode::genRTLIL()`` method returns an ``RTLIL::SigSpec`` structure.
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For nodes that represent expressions (operators, constants, signals, etc.), the
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cells needed to implement the calculation described by the expression are
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created and the resulting signal is returned. That way it is easy to generate
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the circuits for large expressions using depth-first recursion. For nodes that
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do not represent an expression (such as ``AST_CELL``), the corresponding circuit
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is generated and an empty ``RTLIL::SigSpec`` is returned.
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Synthesizing Verilog always blocks
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--------------------------------------
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For behavioural Verilog code (code utilizing ``always``- and ``initial``-blocks)
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it is necessary to also generate ``RTLIL::Process`` objects. This is done in the
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following way:
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Whenever ``AST::AstNode::genRTLIL()`` encounters an ``always``- or
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``initial``-block, it creates an instance of ``AST_INTERNAL::ProcessGenerator``.
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This object then generates the ``RTLIL::Process`` object for the block. It also
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calls ``AST::AstNode::genRTLIL()`` for all right-hand-side expressions contained
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within the block.
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First the ``AST_INTERNAL::ProcessGenerator`` creates a list of all signals
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assigned within the block. It then creates a set of temporary signals using the
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naming scheme ``$ <number> \ <original_name>`` for each of the assigned signals.
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Then an ``RTLIL::Process`` is created that assigns all intermediate values for
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each left-hand-side signal to the temporary signal in its
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``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree.
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Finally a ``RTLIL::SyncRule`` is created for the ``RTLIL::Process`` that assigns
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the temporary signals for the final values to the actual signals.
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A process may also contain memory writes. A ``RTLIL::MemWriteAction`` is created
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for each of them.
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Calls to ``AST::AstNode::genRTLIL()`` are generated for right hand sides as
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needed. When blocking assignments are used, ``AST::AstNode::genRTLIL()`` is
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configured using global variables to use the temporary signals that hold the
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correct intermediate values whenever one of the previously assigned signals is
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used in an expression.
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Unfortunately the generation of a correct
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``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree for behavioural code is a
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non-trivial task. The AST frontend solves the problem using the approach
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described on the following pages. The following example illustrates what the
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algorithm is supposed to do. Consider the following Verilog code:
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.. code:: verilog
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:number-lines:
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always @(posedge clock) begin
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out1 = in1;
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if (in2)
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out1 = !out1;
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out2 <= out1;
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if (in3)
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out2 <= out2;
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if (in4)
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if (in5)
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out3 <= in6;
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else
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out3 <= in7;
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out1 = out1 ^ out2;
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end
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This is translated by the Verilog and AST frontends into the following RTLIL
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code (attributes, cell parameters and wire declarations not included):
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.. code:: RTLIL
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:number-lines:
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cell $logic_not $logic_not$<input>:4$2
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connect \A \in1
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connect \Y $logic_not$<input>:4$2_Y
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end
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cell $xor $xor$<input>:13$3
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connect \A $1\out1[0:0]
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connect \B \out2
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connect \Y $xor$<input>:13$3_Y
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end
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process $proc$<input>:1$1
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assign $0\out3[0:0] \out3
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assign $0\out2[0:0] $1\out1[0:0]
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assign $0\out1[0:0] $xor$<input>:13$3_Y
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switch \in2
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case 1'1
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assign $1\out1[0:0] $logic_not$<input>:4$2_Y
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case
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assign $1\out1[0:0] \in1
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end
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switch \in3
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case 1'1
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assign $0\out2[0:0] \out2
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case
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end
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switch \in4
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case 1'1
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switch \in5
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case 1'1
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assign $0\out3[0:0] \in6
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case
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assign $0\out3[0:0] \in7
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end
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case
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end
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sync posedge \clock
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update \out1 $0\out1[0:0]
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update \out2 $0\out2[0:0]
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update \out3 $0\out3[0:0]
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end
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Note that the two operators are translated into separate cells outside the
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generated process. The signal ``out1`` is assigned using blocking assignments
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and therefore ``out1`` has been replaced with a different signal in all
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expressions after the initial assignment. The signal ``out2`` is assigned using
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nonblocking assignments and therefore is not substituted on the right-hand-side
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expressions.
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The ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree must be interpreted the
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following way:
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- On each case level (the body of the process is the root case), first the
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actions on this level are evaluated and then the switches within the case are
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evaluated. (Note that the last assignment on line 13 of the Verilog code has
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been moved to the beginning of the RTLIL process to line 13 of the RTLIL
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listing.)
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I.e. the special cases deeper in the switch hierarchy override the defaults
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on the upper levels. The assignments in lines 12 and 22 of the RTLIL code
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serve as an example for this.
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Note that in contrast to this, the order within the ``RTLIL::SwitchRule``
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objects within a ``RTLIL::CaseRule`` is preserved with respect to the
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original AST and Verilog code.
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- The whole ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree describes an
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asynchronous circuit. I.e. the decision tree formed by the switches can be
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seen independently for each assigned signal. Whenever one assigned signal
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changes, all signals that depend on the changed signals are to be updated.
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For example the assignments in lines 16 and 18 in the RTLIL code in fact
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influence the assignment in line 12, even though they are in the "wrong
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order".
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The only synchronous part of the process is in the ``RTLIL::SyncRule`` object
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generated at line 35 in the RTLIL code. The sync rule is the only part of the
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process where the original signals are assigned. The synchronization event from
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the original Verilog code has been translated into the synchronization type
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(posedge) and signal (``\clock``) for the ``RTLIL::SyncRule`` object. In the
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case of this simple example the ``RTLIL::SyncRule`` object is later simply
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transformed into a set of d-type flip-flops and the
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``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree to a decision tree using
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multiplexers.
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In more complex examples (e.g. asynchronous resets) the part of the
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``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule`` tree that describes the asynchronous
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reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
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is done by the ``proc_arst`` pass.
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The ProcessGenerator algorithm
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The ``AST_INTERNAL::ProcessGenerator`` uses the following internal state
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variables:
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- | ``subst_rvalue_from`` and ``subst_rvalue_to``
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| These two variables hold the replacement pattern that should be used by
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``AST::AstNode::genRTLIL()`` for signals with blocking assignments. After
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initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are
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empty.
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- | ``subst_lvalue_from`` and ``subst_lvalue_to``
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| These two variables contain the mapping from left-hand-side signals (``\
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<name>``) to the current temporary signal for the same thing (initially
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``$0\ <name>``).
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- | ``current_case``
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| A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case
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of the generated ``RTLIL::Process``.
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As the algorithm runs these variables are continuously modified as well as
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pushed to the stack and later restored to their earlier values by popping from
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the stack.
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On startup the ProcessGenerator generates a new ``RTLIL::Process`` object with
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an empty root case and initializes its state variables as described above. Then
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the ``RTLIL::SyncRule`` objects are created using the synchronization events
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from the AST_ALWAYS node and the initial values of ``subst_lvalue_from`` and
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``subst_lvalue_to``. Then the AST for this process is evaluated recursively.
|
|
|
|
During this recursive evaluation, three different relevant types of AST nodes
|
|
can be discovered: ``AST_ASSIGN_LE`` (nonblocking assignments),
|
|
``AST_ASSIGN_EQ`` (blocking assignments) and ``AST_CASE`` (``if`` or ``case``
|
|
statement).
|
|
|
|
Handling of nonblocking assignments
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
When an ``AST_ASSIGN_LE`` node is discovered, the following actions are
|
|
performed by the ProcessGenerator:
|
|
|
|
- The left-hand-side is evaluated using ``AST::AstNode::genRTLIL()`` and mapped
|
|
to a temporary signal name using ``subst_lvalue_from`` and
|
|
``subst_lvalue_to``.
|
|
|
|
- The right-hand-side is evaluated using ``AST::AstNode::genRTLIL()``. For this
|
|
call, the values of ``subst_rvalue_from`` and ``subst_rvalue_to`` are used to
|
|
map blocking-assigned signals correctly.
|
|
|
|
- Remove all assignments to the same left-hand-side as this assignment from the
|
|
``current_case`` and all cases within it.
|
|
|
|
- Add the new assignment to the ``current_case``.
|
|
|
|
Handling of blocking assignments
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
When an ``AST_ASSIGN_EQ`` node is discovered, the following actions are
|
|
performed by the ProcessGenerator:
|
|
|
|
- Perform all the steps that would be performed for a nonblocking assignment
|
|
(see above).
|
|
|
|
- Remove the found left-hand-side (before lvalue mapping) from
|
|
``subst_rvalue_from`` and also remove the respective bits from
|
|
``subst_rvalue_to``.
|
|
|
|
- Append the found left-hand-side (before lvalue mapping) to
|
|
``subst_rvalue_from`` and append the found right-hand-side to
|
|
``subst_rvalue_to``.
|
|
|
|
Handling of cases and if-statements
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
When an ``AST_CASE`` node is discovered, the following actions are performed by
|
|
the ProcessGenerator:
|
|
|
|
- The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
|
|
``subst_lvalue_from`` and ``subst_lvalue_to`` are pushed to the stack.
|
|
|
|
- A new ``RTLIL::SwitchRule`` object is generated, the selection expression is
|
|
evaluated using ``AST::AstNode::genRTLIL()`` (with the use of
|
|
``subst_rvalue_from`` and ``subst_rvalue_to``) and added to the
|
|
``RTLIL::SwitchRule`` object and the object is added to the ``current_case``.
|
|
|
|
- All lvalues assigned to within the ``AST_CASE`` node using blocking
|
|
assignments are collected and saved in the local variable
|
|
``this_case_eq_lvalue``.
|
|
|
|
- New temporary signals are generated for all signals in
|
|
``this_case_eq_lvalue`` and stored in ``this_case_eq_ltemp``.
|
|
|
|
- The signals in ``this_case_eq_lvalue`` are mapped using ``subst_rvalue_from``
|
|
and ``subst_rvalue_to`` and the resulting set of signals is stored in
|
|
``this_case_eq_rvalue``.
|
|
|
|
Then the following steps are performed for each ``AST_COND`` node within the
|
|
``AST_CASE`` node:
|
|
|
|
- Set ``subst_rvalue_from``, ``subst_rvalue_to``, ``subst_lvalue_from`` and
|
|
``subst_lvalue_to`` to the values that have been pushed to the stack.
|
|
|
|
- Remove ``this_case_eq_lvalue`` from
|
|
``subst_lvalue_from``/``subst_lvalue_to``.
|
|
|
|
- Append ``this_case_eq_lvalue`` to ``subst_lvalue_from`` and append
|
|
``this_case_eq_ltemp`` to ``subst_lvalue_to``.
|
|
|
|
- Push the value of ``current_case``.
|
|
|
|
- Create a new ``RTLIL::CaseRule``. Set ``current_case`` to the new object and
|
|
add the new object to the ``RTLIL::SwitchRule`` created above.
|
|
|
|
- Add an assignment from ``this_case_eq_rvalue`` to ``this_case_eq_ltemp`` to
|
|
the new ``current_case``.
|
|
|
|
- Evaluate the compare value for this case using
|
|
``AST::AstNode::genRTLIL()`` (with the use of ``subst_rvalue_from``
|
|
and ``subst_rvalue_to``) modify the new ``current_case`` accordingly.
|
|
|
|
- Recursion into the children of the ``AST_COND`` node.
|
|
|
|
- Restore ``current_case`` by popping the old value from the stack.
|
|
|
|
Finally the following steps are performed:
|
|
|
|
- The values of ``subst_rvalue_from``, ``subst_rvalue_to``,
|
|
``subst_lvalue_from`` and ``subst_lvalue_to`` are popped from the stack.
|
|
|
|
- The signals from ``this_case_eq_lvalue`` are removed from the
|
|
``subst_rvalue_from``/``subst_rvalue_to``-pair.
|
|
|
|
- The value of ``this_case_eq_lvalue`` is appended to ``subst_rvalue_from`` and
|
|
the value of ``this_case_eq_ltemp`` is appended to ``subst_rvalue_to``.
|
|
|
|
- Map the signals in ``this_case_eq_lvalue`` using
|
|
``subst_lvalue_from``/``subst_lvalue_to``.
|
|
|
|
- Remove all assignments to signals in ``this_case_eq_lvalue`` in
|
|
``current_case`` and all cases within it.
|
|
|
|
- Add an assignment from ``this_case_eq_ltemp`` to ``this_case_eq_lvalue`` to
|
|
``current_case``.
|
|
|
|
Further analysis of the algorithm for cases and if-statements
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
With respect to nonblocking assignments the algorithm is easy: later assignments
|
|
invalidate earlier assignments. For each signal assigned using nonblocking
|
|
assignments exactly one temporary variable is generated (with the ``$0``-prefix)
|
|
and this variable is used for all assignments of the variable.
|
|
|
|
Note how all the ``_eq_``-variables become empty when no blocking assignments
|
|
are used and many of the steps in the algorithm can then be ignored as a result
|
|
of this.
|
|
|
|
For a variable with blocking assignments the algorithm shows the following
|
|
behaviour: First a new temporary variable is created. This new temporary
|
|
variable is then registered as the assignment target for all assignments for
|
|
this variable within the cases for this ``AST_CASE`` node. Then for each case
|
|
the new temporary variable is first assigned the old temporary variable. This
|
|
assignment is overwritten if the variable is actually assigned in this case and
|
|
is kept as a default value otherwise.
|
|
|
|
This yields an ``RTLIL::CaseRule`` that assigns the new temporary variable in
|
|
all branches. So when all cases have been processed a final assignment is added
|
|
to the containing block that assigns the new temporary variable to the old one.
|
|
Note how this step always overrides a previous assignment to the old temporary
|
|
variable. Other than nonblocking assignments, the old assignment could still
|
|
have an effect somewhere in the design, as there have been calls to
|
|
``AST::AstNode::genRTLIL()`` with a
|
|
``subst_rvalue_from``/\ ``subst_rvalue_to``-tuple that contained the
|
|
right-hand-side of the old assignment.
|
|
|
|
The proc pass
|
|
~~~~~~~~~~~~~
|
|
|
|
The ProcessGenerator converts a behavioural model in AST representation to a
|
|
behavioural model in ``RTLIL::Process`` representation. The actual conversion
|
|
from a behavioural model to an RTL representation is performed by the `proc`
|
|
pass and the passes it launches:
|
|
|
|
- | `proc_clean` and `proc_rmdead`
|
|
| These two passes just clean up the ``RTLIL::Process`` structure. The
|
|
`proc_clean` pass removes empty parts (eg. empty assignments) from the
|
|
process and `proc_rmdead` detects and removes unreachable branches from the
|
|
process's decision trees.
|
|
|
|
- | `proc_arst`
|
|
| This pass detects processes that describe d-type flip-flops with
|
|
asynchronous resets and rewrites the process to better reflect what they
|
|
are modelling: Before this pass, an asynchronous reset has two
|
|
edge-sensitive sync rules and one top-level ``RTLIL::SwitchRule`` for the
|
|
reset path. After this pass the sync rule for the reset is level-sensitive
|
|
and the top-level ``RTLIL::SwitchRule`` has been removed.
|
|
|
|
- | `proc_mux`
|
|
| This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to
|
|
a tree of multiplexers per written signal. After this, the
|
|
``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that
|
|
describe the output registers.
|
|
|
|
- | `proc_dff`
|
|
| This pass replaces the ``RTLIL::SyncRule``\ s to d-type flip-flops (with
|
|
asynchronous resets if necessary).
|
|
|
|
- | `proc_memwr`
|
|
| This pass replaces the ``RTLIL::MemWriteAction``\ s with `$memwr` cells.
|
|
|
|
- | `proc_clean`
|
|
| A final call to `proc_clean` removes the now empty ``RTLIL::Process``
|
|
objects.
|
|
|
|
Performing these last processing steps in passes instead of in the Verilog
|
|
frontend has two important benefits:
|
|
|
|
First it improves the transparency of the process. Everything that happens in a
|
|
separate pass is easier to debug, as the RTLIL data structures can be easily
|
|
investigated before and after each of the steps.
|
|
|
|
Second it improves flexibility. This scheme can easily be extended to support
|
|
other types of storage-elements, such as sr-latches or d-latches, without having
|
|
to extend the actual Verilog frontend.
|
|
|
|
.. todo:: Synthesizing Verilog arrays
|
|
|
|
Add some information on the generation of `$memrd` and `$memwr` cells and how
|
|
they are processed in the memory pass.
|
|
|
|
|
|
.. todo:: Synthesizing parametric designs
|
|
|
|
Add some information on the ``RTLIL::Module::derive()`` method and how it is
|
|
used to synthesize parametric modules via the hierarchy pass.
|