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49 lines
2.1 KiB
ReStructuredText
49 lines
2.1 KiB
ReStructuredText
Flow overview
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=============
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.. todo:: less academic
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:numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
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Yosys. Rectangles in the figure represent program modules and ellipses internal
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data structures that are used to exchange design data between the program
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modules.
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Design data is read in using one of the frontend modules. The high-level HDL
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frontends for Verilog and VHDL code generate an abstract syntax tree (AST) that
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is then passed to the AST frontend. Note that both HDL frontends use the same
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AST representation that is powerful enough to cover the Verilog HDL and VHDL
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language.
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The AST Frontend then compiles the AST to Yosys's main internal data format, the
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RTL Intermediate Language (RTLIL). A more detailed description of this format is
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given in :doc:`/yosys_internals/formats/rtlil_rep`.
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There is also a text representation of the RTLIL data structure that can be
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parsed using the RTLIL Frontend which is described in
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:doc:`/appendix/rtlil_text`.
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The design data may then be transformed using a series of passes that all
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operate on the RTLIL representation of the design.
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Finally the design in RTLIL representation is converted back to text by one of
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the backends, namely the Verilog Backend for generating Verilog netlists and the
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RTLIL Backend for writing the RTLIL data in the same format that is understood
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by the RTLIL Frontend.
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With the exception of the AST Frontend, which is called by the high-level HDL
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frontends and can't be called directly by the user, all program modules are
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called by the user (usually using a synthesis script that contains text commands
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for Yosys).
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By combining passes in different ways and/or adding additional passes to Yosys
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it is possible to adapt Yosys to a wide range of applications. For this to be
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possible it is key that (1) all passes operate on the same data structure
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(RTLIL) and (2) that this data structure is powerful enough to represent the
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design in different stages of the synthesis.
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.. figure:: /_images/internals/overview_flow.*
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:class: width-helper invert-helper
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:name: fig:Overview_flow
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Yosys simplified data flow (ellipses: data structures, rectangles:
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program modules)
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