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yosys/techlibs/common
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Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
..
.gitignore
abc9_map.v abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 2020-05-14 16:44:35 -07:00
abc9_model.v abc9_ops/xaiger: further reducing Module::derive() calls by ... 2020-05-14 10:33:57 -07:00
abc9_unmap.v abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 2020-05-14 16:44:35 -07:00
adff2dff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cellhelp.py
cells.lib
cmp2lcu.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cmp2lut.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
dff2ff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
gate2lut.v
gen_fine_ffs.py Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
Makefile.inc abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
mul2dsp.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
pmux2mux.v
prep.cc
simcells.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
simlib.v Add flooring division operator 2020-05-28 22:59:04 +02:00
synth.cc synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
techmap.v Add flooring division operator 2020-05-28 22:59:04 +02:00