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11 lines
212 B
Verilog
11 lines
212 B
Verilog
module test(input [3:0] in, input [1:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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endcase
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endmodule
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