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yosys/techlibs/xilinx
2019-04-22 11:38:23 -07:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
ff_map.v
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
Makefile.inc
synth_xilinx.cc Update help message 2019-04-22 11:38:23 -07:00