mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-16 05:45:47 +00:00
Code Activity
yosys/tests
History
Eddie Hung 587872236e Support and differentiate between ASCII and binary AIG testing
2019-02-08 12:41:59 -08:00
..
aiger Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
asicworld Remove asicworld tests for (unsupported) switch-level modelling 2019-01-27 09:17:02 +01:00
bram
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm
hana
lut cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
memories
opt opt_expr: improve simplification of comparisons with large constants. 2019-01-02 15:45:28 +00:00
realmath
sat
share
simple Extend testcase 2019-02-06 14:02:11 -08:00
simple_defparam Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
smv
sva Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
svinterfaces Add missing .gitignore 2018-12-06 07:29:37 +01:00
techmap
tools Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
unit
various
vloghtb