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yosys/passes
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
..
cmds Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00
equiv equiv_induct: Fix up assumption for $equiv cells in -undef mode. 2020-07-27 18:36:13 +02:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00
memory memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
opt Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 2020-08-20 16:24:53 +02:00
pmgen Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 2020-08-20 16:23:07 +02:00
proc proc: Add -nomux switch 2020-08-20 22:58:08 +02:00
sat async2sync: Support all FF types. 2020-07-30 20:22:03 +02:00
techmap Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00
tests Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00