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00b3c83282
The existing read port assignment algorithm uses Cartesian product expansion, which has O(options^N) complexity. For memories with many read ports (e.g., 64 parallel reads), this causes exponential memory usage (60GB+) and timeouts. This commit adds a beam search algorithm that activates for >8 read ports. It maintains only the top K (default 16) configurations at each step, reducing complexity to O(N * options * K). Tested with: - 64 read ports: completes in ~1s vs OOM - 32 read ports: completes in ~1s vs timeout - Maintains existing behavior for ≤8 ports 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-Authored-By: Claude <noreply@anthropic.com>
27 lines
735 B
Verilog
27 lines
735 B
Verilog
// Test case for beam search optimization in memory_libmap
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// This memory with 32 parallel read ports would cause exponential
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// blowup (O(4^32) = 10^19 configurations) without beam search pruning
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module memlib_beam_search (
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input wire clk,
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input wire we,
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input wire [9:0] wr_addr,
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input wire [7:0] wr_data,
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input wire [9:0] base_addr,
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output reg [255:0] parallel_out // 32 x 8 = 256 bits
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);
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reg [7:0] mem [0:1023];
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integer i;
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always @(posedge clk) begin
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if (we)
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mem[wr_addr] <= wr_data;
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// 32 parallel reads - triggers beam search
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for (i = 0; i < 32; i = i + 1) begin
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parallel_out[i*8 +: 8] <= mem[base_addr + i];
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end
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end
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endmodule
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