mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
11 lines
243 B
Text
11 lines
243 B
Text
# Check wires driven by constants are kept
|
|
read_verilog <<EOT
|
|
module top(output wire [7:0] y);
|
|
assign y = 27;
|
|
endmodule
|
|
EOT
|
|
|
|
equiv_opt -assert bufnorm
|
|
design -load postopt
|
|
select -assert-count 1 t:$buf
|
|
select -assert-count 1 w:y %ci t:$buf %i
|