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https://github.com/YosysHQ/yosys
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120 lines
3.8 KiB
Verilog
120 lines
3.8 KiB
Verilog
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module TopModule(
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input logic clk,
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input logic rst,
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input logic [1:0] sig,
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input logic flip,
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output logic [15:0] passThrough,
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output logic [21:0] outOther,
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input logic interfaceInstanceAtTop_setting,
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output logic [2:0] interfaceInstanceAtTop_other_setting,
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output logic [1:0] interfaceInstanceAtTop_mysig_out,
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output logic [15:0] interfaceInstanceAtTop_passThrough,
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output logic [1:0] sig_out);
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logic MyInterfaceInstance_setting;
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logic [3:0] MyInterfaceInstance_other_setting;
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logic [1:0] MyInterfaceInstance_mysig_out;
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SubModule1 u_SubModule1 (
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.clk(clk),
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.rst(rst),
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.u_MyInterface_setting(MyInterfaceInstance_setting),
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.u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
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.u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
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.u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
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.u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
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.u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
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.u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
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.outOther(outOther),
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.passThrough (passThrough),
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.sig (sig)
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);
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assign sig_out = MyInterfaceInstance_mysig_out;
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assign MyInterfaceInstance_setting = flip;
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endmodule
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module SubModule1(
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input logic clk,
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input logic rst,
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input logic u_MyInterface_setting,
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output logic [3:0] u_MyInterface_other_setting,
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output logic [1:0] u_MyInterface_mysig_out,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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input logic u_MyInterfaceFromTop_setting,
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output logic [2:0] u_MyInterfaceFromTop_other_setting,
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output logic [1:0] u_MyInterfaceFromTop_mysig_out,
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output logic [14:0] u_MyInterfaceFromTop_passThrough,
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output logic [15:0] passThrough
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);
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always @(posedge clk or posedge rst)
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if(rst)
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u_MyInterface_mysig_out <= 0;
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else begin
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if(u_MyInterface_setting)
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u_MyInterface_mysig_out <= sig;
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else
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u_MyInterface_mysig_out <= ~sig;
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end
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logic MyInterfaceInstanceInSub_setting;
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logic [21:0] MyInterfaceInstanceInSub_other_setting;
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logic [1:0] MyInterfaceInstanceInSub_mysig_out;
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assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 : 20;
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SubModule2 u_SubModule2 (
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.clk(clk),
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.rst(rst),
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.u_MyInterfaceInSub2_setting(u_MyInterface_setting),
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.u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
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.u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
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.u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
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.u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
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.u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
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.passThrough (passThrough)
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);
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assign outOther = MyInterfaceInstanceInSub_other_setting;
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assign MyInterfaceInstanceInSub_setting = 0;
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assign MyInterfaceInstanceInSub_mysig_out = sig;
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endmodule
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module SubModule2(
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input logic clk,
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input logic rst,
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input logic u_MyInterfaceInSub2_setting,
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output logic [3:0] u_MyInterfaceInSub2_other_setting,
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input logic [1:0] u_MyInterfaceInSub2_mysig_out,
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input logic u_MyInterfaceInSub3_setting,
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output logic [21:0] u_MyInterfaceInSub3_other_setting,
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input logic [1:0] u_MyInterfaceInSub3_mysig_out,
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output logic [15:0] passThrough
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);
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always @(u_MyInterfaceInSub3_mysig_out) begin
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if (u_MyInterfaceInSub3_mysig_out == 2'b00)
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u_MyInterfaceInSub3_other_setting[21:0] = 1000;
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else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
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u_MyInterfaceInSub3_other_setting[21:0] = 2000;
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else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
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u_MyInterfaceInSub3_other_setting[21:0] = 3000;
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else
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u_MyInterfaceInSub3_other_setting[21:0] = 4000;
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end
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assign passThrough[7:0] = 124;
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assign passThrough[15:8] = 200;
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endmodule
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