mirror of
https://github.com/YosysHQ/yosys
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104 lines
3.2 KiB
Verilog
104 lines
3.2 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// DFFs
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module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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module \$_DFFE_PN1P_ (input D, C, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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// for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
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// and map to intermediate cell types
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module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
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MICROCHIP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
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endmodule
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module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
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MICROCHIP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
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endmodule
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// LATCHES
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module \$_DLATCH_PN0_ (input D, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
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endmodule
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module \$_DLATCH_PN1_ (input D, R, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
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endmodule
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module \$_DLATCH_P_ (input D, E, output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(1'b1), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
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endmodule
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// map intermediate flops to SLE
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`ifdef FINAL_MAP
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module MICROCHIP_SYNC_SET_DFF(
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input D,
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input CLK,
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input Set,
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input En,
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output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
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endmodule
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module MICROCHIP_SYNC_RESET_DFF(
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input D,
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input CLK,
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input Reset,
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input En,
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output Q);
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SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Reset), .SD(1'b0), .LAT(1'b0), .Q(Q));
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endmodule
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`endif
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// LUT
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`ifndef NO_LUT
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
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end else
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if (WIDTH == 2) begin
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CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
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end else
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if (WIDTH == 3) begin
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CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
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end else
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if (WIDTH == 4) begin
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CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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`endif
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