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Code Activity
yosys/frontends
History
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
..
aiger Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ast rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
blif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
json Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
liberty Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
verific Update to latest Verific with extensions for initial assertions 2021-07-09 09:02:27 +02:00
verilog sv: fix a few struct and enum memory leaks 2021-07-06 12:15:08 -04:00