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yosys/techlibs
Marcelina Kościelnicka cde73428b0 Fix syntax error in adff2dff.v
Fixes #2600.
2021-02-24 01:07:34 +01:00
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achronix
anlogic
common Fix syntax error in adff2dff.v 2021-02-24 01:07:34 +01:00
coolrunner2
easic
ecp5
efinix
gowin add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
greenpak4
ice40 verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
intel Fix duplicated parameter name typo 2020-11-18 10:03:57 +01:00
intel_alm intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
machxo2 machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
nexus nexus: Add MULTADDSUB9X9WIDE sim model 2020-12-08 15:49:20 +00:00
sf2
xilinx verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
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