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31 lines
677 B
Text
31 lines
677 B
Text
# Test 1: internal cells from alumacc/techmap must not keep module_not_derived.
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read_verilog <<EOF_VERILOG
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module top(a, b, y);
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input wire [7:0] a;
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input wire [7:0] b;
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output wire [7:0] y;
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assign y = a + b;
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endmodule
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EOF_VERILOG
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prep
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alumacc
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techmap -max_iter 1
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select -assert-any t:$lcu
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select -assert-count 0 t:$lcu a:module_not_derived %i
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design -reset
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# Test 2: public module instances should still keep module_not_derived.
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read_verilog <<EOF_VERILOG
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module mycell(input a, output y);
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assign y = a;
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endmodule
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module top(input a, output y);
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mycell u0(.a(a), .y(y));
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endmodule
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EOF_VERILOG
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hierarchy -top top
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select -assert-any t:mycell a:module_not_derived %i
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