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29 lines
688 B
Text
29 lines
688 B
Text
read_verilog <<EOT
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module top(
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input signed [7:0] A,
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input signed [7:0] D,
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input signed [7:0] B,
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output signed [16:0] P
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);
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assign P = (A - D) * B;
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endmodule
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EOT
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proc
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design -save gold
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synth_xilinx -noiopad
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design -save gate
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cd top
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select -assert-count 1 t:DSP48E1
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select -assert-count 1 t:DSP48E1 r:USE_DPORT=TRUE %i
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select -assert-none t:DSP48E1 %% t:* %D
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# Now prove functional equivalence of the mapped netlist against the original
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# (saved as `gold` above).
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design -reset
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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techmap -wb -D EQUIV -autoproc -map +/xilinx/cells_sim.v
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equiv_make gold gate equiv
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equiv_induct equiv
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equiv_status -assert equiv
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