3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 16:45:32 +00:00
yosys/tests/various/design2.ys
2020-04-16 08:05:18 -07:00

9 lines
186 B
Text

read_verilog <<EOT
module top(input i, output o);
assign o = i;
endmodule
EOT
design -stash foo
design -delete foo
logger -expect error "No saved design 'foo' found!" 1
design -load foo