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https://github.com/YosysHQ/yosys
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156 lines
No EOL
2.6 KiB
Systemverilog
156 lines
No EOL
2.6 KiB
Systemverilog
// https://github.com/YosysHQ/yosys/issues/5917
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module mul18_pipe(
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_pipe_signed (
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input logic clk,
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input logic signed [17:0] a,
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input logic signed [17:0] b,
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output logic signed [35:0] y
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);
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logic signed [17:0] a_r;
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logic signed [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_pipe_in_only (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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end
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assign y = a_r * b_r;
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endmodule
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module mul18_pipe_out_only (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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always_ff @(posedge clk)
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y <= a * b;
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endmodule
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module mul18_pipe_io_rst (
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input logic clk,
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input logic rst,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk)
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if (rst) begin a_r <= 0; b_r <= 0; y <= 0; end
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else begin a_r <= a; b_r <= b; y <= a_r * b_r; end
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endmodule
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module mul24_io (
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input logic clk,
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input logic [23:0] a,
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input logic [23:0] b,
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output logic [47:0] y
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);
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logic [23:0] a_r;
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logic [23:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul32_io (
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input logic clk,
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input logic [31:0] a,
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input logic [31:0] b,
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output logic [63:0] y
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);
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logic [31:0] a_r;
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logic [31:0] b_r;
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always_ff @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_negedge (
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input logic clk,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(negedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul18_rst_nonzero (
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input logic clk,
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input logic rst,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk)
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if (rst) begin a_r <= 18'h3; b_r <= 18'h7; end
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else begin a_r <= a; b_r <= b; end
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always_ff @(posedge clk)
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y <= a_r * b_r;
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endmodule
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module mul18_two_clock (
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input logic clk0,
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input logic clk1,
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input logic [17:0] a,
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input logic [17:0] b,
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output logic [35:0] y
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);
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logic [17:0] a_r;
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logic [17:0] b_r;
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always_ff @(posedge clk0) a_r <= a;
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always_ff @(posedge clk1) b_r <= b;
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assign y = a_r * b_r;
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endmodule |