mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 11:26:22 +00:00
52 lines
668 B
CMake
52 lines
668 B
CMake
yosys_pass(synth_intel
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synth_intel.cc
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REQUIRES
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abc
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abc9
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autoname
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blackbox
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check
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clean
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deminout
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dfflegalize
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flatten
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fsm
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hierarchy
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iopadmap
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memory
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memory_bram
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memory_map
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opt
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opt_clean
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opt_expr
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peepopt
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proc
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read_verilog
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setundef
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stat
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techmap
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tribuf
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wreduce
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write_blif
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write_verilog
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DATA_DIR
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intel
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DATA_FILES
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common/m9k_bb.v
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common/altpll_bb.v
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common/brams_m9k.txt
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common/brams_map_m9k.v
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common/ff_map.v
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max10/cells_sim.v
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max10/cells_map.v
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cyclone10lp/cells_sim.v
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cyclone10lp/cells_map.v
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cycloneiv/cells_sim.v
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cycloneiv/cells_map.v
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cycloneive/cells_sim.v
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cycloneive/cells_map.v
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)
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