mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 18:05:24 +00:00
0f13b55173
This adds optional in-memory caching of parsed liberty files to speed up flows that repeatedly parse the same liberty files. To avoid increasing the memory overhead by default, the caching is disabled by default. The caching can be controlled globally or on a per path basis using the new `libcache` command, which also allows purging cached data.
422 lines
13 KiB
C++
422 lines
13 KiB
C++
#include "kernel/yosys.h"
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#include "kernel/ff.h"
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#include "kernel/gzip.h"
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#include "libparse.h"
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#include <optional>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ClockGateCell {
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IdString name;
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IdString ce_pin;
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IdString clk_in_pin;
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IdString clk_out_pin;
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std::vector<IdString> tie_lo_pins;
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};
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ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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ClockGateCell c;
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c.name = RTLIL::escape_id(name);
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char delimiter = ':';
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size_t pos1 = str.find(delimiter);
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if (pos1 == std::string::npos)
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log_cmd_error("Not enough ports in descriptor string");
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size_t pos2 = str.find(delimiter, pos1 + 1);
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if (pos2 == std::string::npos)
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log_cmd_error("Not enough ports in descriptor string");
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size_t pos3 = str.find(delimiter, pos2 + 1);
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if (pos3 != std::string::npos)
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log_cmd_error("Too many ports in descriptor string");
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std::string ce = str.substr(0, pos1);
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c.ce_pin = RTLIL::escape_id(ce);
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std::string clk_in = str.substr(pos1 + 1, pos2 - (pos1 + 1));
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c.clk_in_pin = RTLIL::escape_id(clk_in);
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std::string clk_out = str.substr(pos2 + 1, str.size() - (pos2 + 1));
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c.clk_out_pin = RTLIL::escape_id(clk_out);
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return c;
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}
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static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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find_icgs(std::vector<const LibertyAst *> cells, std::vector<std::string> const& dont_use_cells) {
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// We will pick the most suitable ICG absed on tie_lo count and area
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struct ICGRankable : public ClockGateCell { double area; };
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std::optional<ICGRankable> best_pos;
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std::optional<ICGRankable> best_neg;
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// This is a lot of boilerplate, isn't it?
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for (auto cell : cells)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (auto dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *icg_kind_ast = cell->find("clock_gating_integrated_cell");
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if (icg_kind_ast == nullptr)
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continue;
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auto cell_name = cell->args[0];
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auto icg_kind = icg_kind_ast->value;
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auto starts_with = [&](std::string prefix) {
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return icg_kind.compare(0, prefix.size(), prefix) == 0;
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};
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bool clk_pol;
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if (icg_kind == "latch_posedge" || starts_with("latch_posedge_")) {
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clk_pol = true;
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} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
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clk_pol = false;
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} else {
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log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
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continue;
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}
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log_debug("maybe valid icg: %s\n", cell_name.c_str());
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ClockGateCell icg_interface;
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icg_interface.name = RTLIL::escape_id(cell_name);
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for (auto pin : cell->children) {
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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if (pin->find("clock_gate_clock_pin")) {
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if (!icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
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} else if (pin->find("clock_gate_out_pin")) {
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if (!icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
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} else if (pin->find("clock_gate_enable_pin")) {
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if (!icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
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} else if (pin->find("clock_gate_test_pin")) {
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icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
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} else {
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const LibertyAst *dir = pin->find("direction");
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if (dir->value == "internal")
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continue;
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log_warning("Malformed liberty file - extra pin %s in cell %s\n",
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pin->args[0].c_str(), cell_name.c_str());
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continue;
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}
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}
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if (icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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if (icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_out_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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if (icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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std::optional<ICGRankable>& icg_to_beat = clk_pol ? best_pos : best_neg;
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bool winning = false;
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if (icg_to_beat) {
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log_debug("ties: %zu ? %zu\n", icg_to_beat->tie_lo_pins.size(),
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icg_interface.tie_lo_pins.size());
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log_debug("area: %f ? %f\n", icg_to_beat->area, area);
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// Prefer fewer test enables over area reduction (unlikely to matter)
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auto goal = std::make_pair(icg_to_beat->tie_lo_pins.size(), icg_to_beat->area);
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auto cost = std::make_pair(icg_interface.tie_lo_pins.size(), area);
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winning = cost < goal;
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if (winning)
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log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str());
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} else {
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log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
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winning = true;
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}
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if (winning) {
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ICGRankable new_icg {icg_interface, area};
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icg_to_beat.emplace(new_icg);
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}
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}
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std::optional<ClockGateCell> pos;
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std::optional<ClockGateCell> neg;
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if (best_pos) {
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log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
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pos.emplace(*best_pos);
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}
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if (best_neg) {
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log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
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neg.emplace(*best_neg);
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}
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return std::make_pair(pos, neg);
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}
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struct ClockgatePass : public Pass {
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ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
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void help() override {
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clockgate [options] [selection]\n");
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log("\n");
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log("This pass transforms each set of FFs sharing the same clock and\n");
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log("enable signal into a clock-gating cell and a set of enable-less FFs.\n");
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log("Primarily a power-saving transformation on ASIC designs.\n");
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log("\n");
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log(" -pos <celltype> <ce>:<clk>:<gclk>\n");
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log(" If specified, rising-edge FFs will have CE inputs\n");
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log(" removed and a gated clock will be created by the\n");
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -neg <celltype> <ce>:<clk>:<gclk>\n");
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log(" If specified, falling-edge FFs will have CE inputs\n");
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log(" removed and a gated clock will be created by the\n");
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -liberty <filename>\n");
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log(" If specified, ICGs will be selected from the liberty files\n");
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log(" if available. Priority is given to cells with fewer tie_lo\n");
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log(" inputs and smaller size. This removes the need to manually\n");
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log(" specify -pos or -neg and -tie_lo.\n");
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log(" -dont_use <celltype>\n");
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log(" Cells <celltype> won't be considered when searching for ICGs\n");
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log(" in the liberty file specified by -liberty.\n");
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log(" -tie_lo <port_name>\n");
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log(" Port <port_name> of the ICG will be tied to zero.\n");
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log(" Intended for DFT scan-enable pins.\n");
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log(" -min_net_size <n>\n");
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log(" Only transform sets of at least <n> eligible FFs.\n");
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log(" \n");
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}
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// One ICG will be generated per ClkNetInfo
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// if the number of FFs associated with it is sufficent
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struct ClkNetInfo {
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// Original, ungated clock into enabled FF
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SigBit clk_bit;
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// Original clock enable into enabled FF
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SigBit ce_bit;
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bool pol_clk;
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bool pol_ce;
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[[nodiscard]] Hasher hash_into(Hasher h) const {
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auto t = std::make_tuple(clk_bit, ce_bit, pol_clk, pol_ce);
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h.eat(t);
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return h;
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}
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bool operator==(const ClkNetInfo& other) const {
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return (clk_bit == other.clk_bit) &&
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(ce_bit == other.ce_bit) &&
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(pol_clk == other.pol_clk) &&
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(pol_ce == other.pol_ce);
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}
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};
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struct GClkNetInfo {
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// How many CE FFs on this CLK net have we seen?
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int net_size;
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// After ICG generation, we have new gated CLK signals
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Wire* new_net;
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};
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ClkNetInfo clk_info_from_ff(FfData& ff) {
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SigBit clk = ff.sig_clk[0];
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SigBit ce = ff.sig_ce[0];
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ClkNetInfo info{clk, ce, ff.pol_clk, ff.pol_ce};
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return info;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing CLOCK_GATE pass (extract clock gating out of flip flops).\n");
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::vector<std::string> tie_lo_pins;
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std::vector<std::string> liberty_files;
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std::vector<std::string> dont_use_cells;
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int min_net_size = 0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-pos" && argidx+2 < args.size()) {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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pos_icg_desc = icg_from_arg(name, rest);
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continue;
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}
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if (args[argidx] == "-neg" && argidx+2 < args.size()) {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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neg_icg_desc = icg_from_arg(name, rest);
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continue;
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}
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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std::string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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liberty_files.push_back(liberty_file);
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continue;
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}
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if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {
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dont_use_cells.push_back(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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if (!liberty_files.empty()) {
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LibertyMergedCells merged;
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for (auto path : liberty_files) {
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std::istream* f = uncompressed(path);
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if (f->fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
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LibertyParser p(*f, path);
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merged.merge(p);
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delete f;
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}
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std::tie(pos_icg_desc, neg_icg_desc) =
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find_icgs(merged.cells, dont_use_cells);
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} else {
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for (auto pin : tie_lo_pins) {
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if (pos_icg_desc)
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pos_icg_desc->tie_lo_pins.push_back(pin);
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if (neg_icg_desc)
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neg_icg_desc->tie_lo_pins.push_back(pin);
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}
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}
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extra_args(args, argidx, design);
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pool<Cell*> ce_ffs;
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dict<ClkNetInfo, GClkNetInfo> clk_nets;
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int gated_flop_count = 0;
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for (auto module : design->selected_whole_modules()) {
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for (auto cell : module->cells()) {
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(nullptr, cell);
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// It would be odd to get constants, but we better handle it
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if (ff.has_ce) {
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if (!ff.sig_clk.is_bit() || !ff.sig_ce.is_bit())
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continue;
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if (!ff.sig_clk[0].is_wire() || !ff.sig_ce[0].is_wire())
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continue;
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ce_ffs.insert(cell);
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ClkNetInfo info = clk_info_from_ff(ff);
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auto it = clk_nets.find(info);
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if (it == clk_nets.end())
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clk_nets[info] = GClkNetInfo();
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clk_nets[info].net_size++;
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}
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}
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for (auto& clk_net : clk_nets) {
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auto& clk = clk_net.first;
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auto& gclk = clk_net.second;
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if (gclk.net_size < min_net_size)
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continue;
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std::optional<ClockGateCell> matching_icg_desc;
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if (pos_icg_desc && clk.pol_clk)
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matching_icg_desc = pos_icg_desc;
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else if (neg_icg_desc && !clk.pol_clk)
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matching_icg_desc = neg_icg_desc;
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if (!matching_icg_desc)
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continue;
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Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
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icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
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icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
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gclk.new_net = module->addWire(NEW_ID);
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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// Tie low DFT ports like scan chain enable
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for (auto port : matching_icg_desc->tie_lo_pins)
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icg->setPort(port, Const(0, 1));
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// Fix CE polarity if needed
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if (!clk.pol_ce) {
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SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
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icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
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}
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}
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for (auto cell : ce_ffs) {
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FfData ff(nullptr, cell);
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ClkNetInfo info = clk_info_from_ff(ff);
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auto it = clk_nets.find(info);
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log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets");
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if (!it->second.new_net)
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continue;
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log_debug("Fix up FF %s\n", cell->name.c_str());
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// Now we start messing with the design
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ff.has_ce = false;
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// Construct the clock gate
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// ICG = integrated clock gate, industry shorthand
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ff.sig_clk = (*it).second.new_net;
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// Rebuild the flop
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(void)ff.emit();
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gated_flop_count++;
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}
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ce_ffs.clear();
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clk_nets.clear();
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}
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log("Converted %d FFs.\n", gated_flop_count);
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}
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} ClockgatePass;
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PRIVATE_NAMESPACE_END
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