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13 lines
216 B
Verilog
13 lines
216 B
Verilog
module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [2:0] count;
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always @(posedge clk)
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if (rst)
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count <= 3'd0;
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else if (en)
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count <= count + 3'd1;
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endmodule
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