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yosys/backends/verilog
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Krystine Sherwin fcb8695261
write_verilog: Skip empty switches
2026-01-07 13:09:49 +13:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: Skip empty switches 2026-01-07 13:09:49 +13:00
verilog_backend.h rename: add -unescape 2025-06-24 12:33:33 +02:00