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646ff6d32d
More `literalinclude` and references to source. Adding `example_show.ys` and `example_lscd.ys`. Rename `example_00` et al to `example_first` et al. Also some other minor tidying.
6 lines
150 B
Text
6 lines
150 B
Text
read_verilog example.v
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show -format dot -prefix example_first
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proc
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show -format dot -prefix example_second
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opt
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show -format dot -prefix example_third
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