mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 16:45:32 +00:00
3 lines
131 B
Verilog
3 lines
131 B
Verilog
module \$__EFX_GBUF (input I, output O);
|
|
EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));
|
|
endmodule
|