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lofty/quicklogic-mem-clk
yosys
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passes
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sat
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Martin Povišer
1b1a6c4aed
Merge pull request
#4525
from georgerennie/peepopt_clock_gate
...
peepopt: Add formal opt to rewrite latches to ffs in clock gates
2024-11-11 14:49:09 +01:00
..
assertpmux.cc
async2sync.cc
clk2fflogic.cc
cutpoint.cc
eval.cc
example.v
example.ys
expose.cc
fmcombine.cc
fminit.cc
formalff.cc
freduce.cc
Makefile.inc
miter.cc
mutate.cc
qbfsat.cc
qbfsat.h
recover_names.cc
sat.cc
sim.cc
supercover.cc
synthprop.cc