mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 08:35:32 +00:00
8611429237
* ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
3 lines
76 B
Text
3 lines
76 B
Text
read_verilog bug3670.v
|
|
read_verilog -lib -specify +/xilinx/cells_sim.v
|
|
abc9
|