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13 lines
498 B
Text
13 lines
498 B
Text
read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/analogdevices/cells_sim.v -map +/simcells.v synth_analogdevices # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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select -assert-count 2 t:INBUF
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select -assert-count 1 t:INV
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select -assert-count 1 t:OBUFT
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select -assert-none t:INBUF t:INV t:OBUFT %% t:* %D
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