mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-12 23:46:40 +00:00
c2b7ad3b28
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2 lines
30 B
Text
2 lines
30 B
Text
brams_init.mk
|
|
brams_init_*.vh
|