mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
f965b3fa54
Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
14 lines
155 B
Text
14 lines
155 B
Text
read_rtlil << EOT
|
|
|
|
module \top
|
|
wire output 1 \a
|
|
wire width 0 $dummy
|
|
cell \abc \abc
|
|
connect \a \a
|
|
connect \b $dummy
|
|
end
|
|
end
|
|
|
|
EOT
|
|
|
|
opt_clean
|