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22 lines
289 B
Systemverilog
22 lines
289 B
Systemverilog
module top(input i, output o);
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A A();
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B B();
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assign A.i = i;
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assign o = B.o;
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always @* assert(o == i);
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endmodule
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module A;
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wire i, y;
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`ifdef FAIL
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assign B.x = i;
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`else
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assign B.x = !i;
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`endif
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assign y = !B.y;
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endmodule
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module B;
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wire x, y, o;
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assign y = x, o = A.y;
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endmodule
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