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13 lines
210 B
Verilog
13 lines
210 B
Verilog
module lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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input [WIDTH-1:0] P, G;
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input CI;
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output [WIDTH-1:0] CO;
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reg [WIDTH-1:0] p, g;
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\$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO));
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endmodule
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